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Silicon Test and Yield Analysis Resources

IEEE Conference Papers

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STIL Checker

STILVerify is the first commercially available syntax checker and verification tool for the STIL language, enabling developers of ATE, EDA and related tools to ensure compatibility with STIL-based flows. Download STIL Verify for free today. More

Success Story

Renesas Technology approached this multi-faceted problem with a multifaceted answer, one that begins with Mentor Graphics TestKompress solution. View Success Story

Partner Programs

Mentor Graphics silicon test solutions works closely with leading ATE vendors, fabless semiconductor companies and our affiliates to provide a complete set of design-for-test solutions for our customers. View existing Partners

If you are interested in becoming a Silicon Test and Yield Analysis partner, please email us at

Recommended Papers

Read about the latest, innovative techniques in subjects such as proven DFT solutions, high quality test, compression solutions and yield improvements. These articles and conference papers will give you insight on Mentor Graphics technology.

Proven Silicon Test and Yield Analysis Solutions

Mentor's Tessent products are used effectively in billions of devices. Even products that are considered relatively new are already used in over a billion devices and over one thousand designs. All Mentor Tessent tools (including Tessent TestKompress and Tessent Diagnosis) are recommended in the latest TSMC and UMC reference flows.

Most Effective Compression

Tessent TestKompress provides the highest level of compression possible. This compression not only dramatically reduces test time (and data) but can also be used for dramatic reduction of test pins and signals. In fact, as few as 1 scan channel can be used within Tessent TestKompress blocks.

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