Silicon Test and Yield Analysis Resources
IEEE Conference Papers
This material is posted here with permission of the IEEE, SEMI and/or ASM International. Such permission does not in any way imply endorsement of any of Mentor Graphics's products or services. Internal or personal use of this material is permitted.
However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE, SEMI and/or ASM International by writing to firstname.lastname@example.org or ASM International, Materials Park, Ohio, USA 44073-0002. View existing papers
STILVerify is the first commercially available syntax checker and verification tool for the STIL language, enabling developers of ATE, EDA and related tools to ensure compatibility with STIL-based flows. Download STIL Verify for free today. More
Renesas Technology approached this multi-faceted problem with a multifaceted answer, one that begins with Mentor Graphics TestKompress solution. View Success Story
Mentor Graphics silicon test solutions works closely with leading ATE vendors, fabless semiconductor companies and our affiliates to provide a complete set of design-for-test solutions for our customers. View existing Partners
If you are interested in becoming a Silicon Test and Yield Analysis partner, please email us at email@example.com.
Read about the latest, innovative techniques in subjects such as proven DFT solutions, high quality test, compression solutions and yield improvements. These articles and conference papers will give you insight on Mentor Graphics technology.
Proven Silicon Test and Yield Analysis Solutions
Mentor's Tessent products are used effectively in billions of devices. Even products that are considered relatively new are already used in over a billion devices and over one thousand designs. All Mentor Tessent tools (including Tessent TestKompress and Tessent Diagnosis) are recommended in the latest TSMC and UMC reference flows.
- Renesas Technology Proves Success with Mentor Graphics TestKompress and a Customized Test Approach
Customer Success Story
- Reducing The Design Impact Of DFT In The Nanometer Era
Most Effective Compression
Tessent TestKompress provides the highest level of compression possible. This compression not only dramatically reduces test time (and data) but can also be used for dramatic reduction of test pins and signals. In fact, as few as 1 scan channel can be used within Tessent TestKompress blocks.
- X-Press Compactor for 1000x Reduction of Test Data
- Embedded Compression for Production Test