IC designs at 14nm will have new structures and new techniques that impact routing, design for manufacturing, extraction and verification. Designers will need new models for both local interconnect and device-level structures like FinFets. They will also need efficient ways to handle colored vs. non-colored double patterning data, and more extensive corner management. Simple dummy fill or router track fill will not work at 14 nm due to fill impacts on lithography, rapid temperature annealing (RTA), stress and many other effects. Designers may be required to use proscriptive design rules. This panel will discuss the intricacies of IC design at 14nm and how the design enabling and manufacturing flow will change to meet the new physical challenges.
• Moderator: Paul Dempsey, Editor-In-Chief, Tech Design Forum
• Jean-Pierre Geronimi, Special Project Director in Central CAD and Design Solutions, STMicroelectronics
• Dipesh Patel, Deputy General Manager, Physical IP Division, ARM
• Joseph Sawicki, VP and GM Design to Silicon Division, Mentor Graphics
• Lars Liebmann, Distinguished Engineer, IBM