Design Flows Using TestKompress
Mentor Test Announcements at 2013 ITC
Steve Pateras talks to EDA Café about what's new and hot in test from Mentor.
Improve Logic Test with a Hybrid ATPG/BIST Solution
Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a...
Automated Test Creation for Mixed Signal IP using IJTAG
The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embedded IP, the new IEEE P1687 standard 1 is being...