Large System on Chip (SoC) designs present many challenges to all design disciplines, including design-for-test (DFT). By taking a divide-and-conquer approach to test, significant savings in tool runtime and memory consumption can be realized. This whitepaper describes the basic components of a hierarchical DFT methodology, the benefits that it provides, and the tool automation that is available through Mentor’s Tessent tool suite. For large SoC devices, the front-end and physical design practices are typically performed at a core level. Whether it’s called a core, block, tile, macro, or module they all refer to the level of hierarchy at which design tasks are completed. These completed cores are then integrated into the SoC. Hierarchical DFT refers to the practice of implementing all DFT with respect to these same core hierarchical boundaries. The test patterns for these cores are then applied individually or in groups from the SoC level. With hierarchical DFT, once a core design is complete it means it’s DFT complete as well, and that it includes a set of patterns that can be used to test the core regardless of how it gets integrated into an SoC. Cores can be tested individually, in groups or all together; whatever best suits the test plan and available pin resources in the SoC. Interconnect between cores and chip-level glue logic are then tested separately and the coverage for all test modes is combined into a single comprehensive coverage report. A hierarchical DFT methodology solves many issues that are often encountered with the insertion of DFT structures and running ATPG for large SoCs. The best way to address the challenges of testing large SoCs is to take a divide-and-conquer approach that cuts the task down into smaller, more manageable pieces. This whitepaper highlights the key DFT tasks required for hierarchical DFT and how they fit into the overall flow.
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ATPG, embedded compression, hierarchical test, IC Design, IC test, scan test, semiconductor test, Silicon Test, Tessent, test pattern