In this whitepaper, we explore how a layout- aware diagnosis is a powerful tool for both failure analysis engineers, who find the root cause of a particular failing die, and for yield engineers, who need sets of diagnosis data to find the systematic yield limiters across the life of the product.
Logic-based scan test diagnosis is an established software-based methodology for finding the defect location in a failing die. Using structural test patterns (such as ATPG) and the design description, diagnosis turns failing test cycles into valuable data. However, even with significant recent improvements in scan logic diagnosis algorithms, there is a gap between what scan logic diagnosis can deliver and what failure analysis (FA) and yield engineers need. The technology that makes scan diagnosis indispensable is called layout-aware diagnosis because it matches the traditional diagnosis results with physical locations on the chip. This enables correlation of diagnosis results with other design profiling information like design rule (DRC) and lithographic (DFM) violations. By leveraging the physical design information during the diagnosis process, as Mentor’s Tessent® Diagnosis does, you can improve the accuracy and resolution of diagnosis results by 70% to 85% over purely logic-based scan diagnosis, depending on the defect type.