Through-silicon vias (TSV) are a popular choice for implementing three-dimensional integrated circuits (3DIC). However, introducing TSVs impacts signal integrity, longest path delay, and power consumption. For high performance designs, noise on the TSV nets makes it difficult to control clock skew and estimate cell delay. For low power applications, the supply voltage is lower than for normal circuits, making coupling noise on critical nets a threat to the whole system. Therefore, a precise estimation of the TSV impact on the whole system is essential. A new extraction model and methods can reduce coupling noise by more than 25%, with minimal overhead.