Scan logic diagnosis turns failing test cycles into valuable data and is an established method for digital semiconductor defect localization. The advent of layout-aware scan diagnosis represented a dramatic advance in diagnosis technology because it reduces suspect area by up to 85% and identifies physical net segments rather than entire logic nets [1-3]. The defect classifications provided by layout-aware diagnosis make diagnosis an effective tool not just for localization of defects but also for yield analysis. Diagnosis-driven yield analysis (DDYA) makes volume diagnosis results actionable by identifying the most likely causes of yield. Layout-aware diagnosis also has its limits; a diagnosis result may point to multiple locations and one single location could be explained by multiple root causes. For instance, an open in a particular net segment could be explained by an open defect in metal 2 of that segment, an open in metal3, a single via3, or a double via3. In other words, there is a certain amount of ambiguity or noise in the diagnosis results. Root Cause Deconvolution (RCD), a statistical enhancement technology recently made available in the Tessent Diagnosis and Tessent YieldInsight products, is the next step in diagnosis resolution enhancement. It works by analyzing multiple layout-aware diagnosis reports together to identify the underlying defect distribution (root cause distribution) that is most likely to explain this set of diagnosis results. The results are then back-annotated to the individual diagnosis suspects. Where layout-aware diagnosis points to a segment, RCD can isolate a particular root cause in that segment. This increase in the FA relevance and success rate dramatically reduces the failure analysis (FA) cycle time from months to days. RCD also enables “virtual FA”, the ability to determine defect distribution for a population of failing devices before any failure analysis is performed. Later in this whitepaper, we will also review silicon results.