By the time a serious lithographic problem is identified at the fab, it is too late in the design process to make a simple layout change, resulting in a significant delay of the tapeout, and consequently chip delivery. To diminish the risk of sensitive layout structures, and avoid or reduce design delays, designers need the capability to detect printability issues as early as possible in the design flow.
Calibre® LFD™ is a lithography simulation tool that detects layout lithography weak points and analyzes the effect of lithography on the design’s electrical performance. It considers resolution enhancement techniques and other pattern transfer processes to determine the robustness of a given layout to manufacturing variations. This paper discusses the technical aspects of adopting Calibre LFD in the design flow, and presents the results and returns of three years of cooperation between Mentor Graphics and Infineon Technologies.