Silicon Learning

The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases. The products provide solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis. Combining statistical analysis and scan diagnosis has been shown to reduce time to root cause of yield loss.

Scan Test Diagnosis of Defects in Semiconductor Devices

Scan Test Diagnosis of Defects in Semiconductor Devices

Technology Overview At this year's ISTFA Exposition, Mentor Graphics' Geir Eide, Product Marketing Manager, talks about/demonstrates Scan Test Diagnosis of Defects in Semiconductor Devices. The International Symposium on Testing...

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Products

  • Tessent SiliconInsight

    Tessent® SiliconInsight® provides an automated interactive environment for test bring-up, debug, and silicon characterization of devices containing Tessent BIST capabilities. It can greatly increase productivity for chip designers and test engineers during silicon validation and debug, speeding time-to-market. Tessent SiliconInsight reduces test and silicon bring-up time with interactive debug and characterization for benchtop environments.

  • Tessent Diagnosis

    Tessent® Diagnosis performs accurate and high-resolution test failure diagnosis to determine a defect’s most probable failure mechanism, logic location, and physical location. The tool uses failure data from manufacturing test, scan test patterns, and design information. With this data, Tessent Diagnosis identifies the location and classification of the defect causing the failure.

  • Tessent YieldInsight

    Tessent® YieldInsight statistically analyzes diagnosis data to identify and separate systematic yield limiters before failure analysis. This eliminates the need for costly physical localization and reduces the time to determining root cause of yield loss from weeks to days. Selection of die for failure analysis is facilitated by automatically identifying die that clearly exhibit the identified systematic issues.

Technology Overviews

Scan Test Diagnosis in Electronics Failure Analysis

Scan Test Diagnosis in Electronics Failure Analysis

Technology Overview At this year's ISTFA Exposition, Mentor Graphics' Geir Eide, Product Marketing Manager, talks about/demonstrates Scan Test Diagnosis in Electronics Failure Analysis. The International Symposium on Testing...

View Video
Scan Test Diagnosis of Defects in Semiconductor Devices

Scan Test Diagnosis of Defects in Semiconductor Devices

Technology Overview At this year's ISTFA Exposition, Mentor Graphics' Geir Eide, Product Marketing Manager, talks about/demonstrates Scan Test Diagnosis of Defects in Semiconductor Devices. The International Symposium on Testing...

View Video
Interactive Diagnostics with Tessent Silicon Insight Desktop

Interactive Diagnostics with Tessent Silicon Insight Desktop

Technology Overview This demo shows how to perform interactive silicon debug and characterization with the desktop version.

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Yield Learning with Tessent Diagnosis and Tessent YieldInsight

Yield Learning with Tessent Diagnosis and Tessent YieldInsight

Technology Overview Indentifying the root cause of yield loss can take weeks or months using traditional methods. Learn how using the Tessent yield analysis solutions will significantly shorten this time.

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Tessent IJTAG—Automation of the IEEE P1687 Standard Datasheet (PDF, 963kb)

Datasheets

Toolbox

Tessent Training

We have training courses available for Tessent products in our training centers around the world, online, or at your site.

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Manufacturing Variability Solutions

Yield Ramp

With diagnosis-driven yield analysis, you can rapidly narrow down the most likely cause of failures, enabling you to take timely corrective actions in the manufacturing process or changes to the design that impact product yield rates. Yield Ramp