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Renesas Technology is a semiconductor company that leads the way in manufacturing test methods and improving the quality of the products they ship to customers. Renesas Technology has been developing systems-on-chip (SoCs) at the 130nm and 90nm and is now ramping up for 65nm. Design sizes range from one million to 10 million gates, depending on the application. While 10X compression has been sufficient for SoCs at larger geometries, greater compression was needed at 90nm. And with 65nm on the horizon, Renesas Technology looked to Mentor Graphics test tools to manage the challenges.

Efficient and higher compressed test patterns helps minimize the time and effort it takes to deliver our advanced SoC and microcontroller solutions. We also have high expectations on improving our product quality by using TestKompress at-speed solutions.”

Osamu Tada, Department Manager, System Level Design and Verification, Technology Department, Renesas Technology Corp.

Renesas Technology, like other semiconductor companies, faces the universal challenges of increasing design size, shrinking geometries, increased functionality, increased test pattern volume, pressure on time to market, and concern for costs. ATE investment is restrained just as pattern volume is exceeding the memory size in ATE. As a result, a tester cannot store patterns to the memory with onetime loading for large SoCs. If the remaining patterns were re-loaded in the tester, the testing time and cost would increase.

And what about test quality? While the stuck-at fault model is the traditional approach for larger geometries, smaller designs are showing new defects, such as resistive opens, and delay defects are increasing. Unfortunately, stuck-at patterns cannot detect these defects.

That's why at-speed test is being implemented for the effective detection of nanometer design defects.

Yet, at-speed test is only part of the solution. Design size increases result in test pattern increases. A high-capacity test is required, but is often prohibitively expensive. Multiple load testing is an alternative, but test time increases. Test quality, however, needs improvement in order to detect the new defects. Again, though, new tester equipment is expensive and additional at-speed test pattern increases test time. All of this contributes to a higher-priced chip, and perhaps, the loss of a market window.

Renesas Technology approached this multi-faceted problem with a multifaceted answer, one that begins with Mentor Graphics TestKompress solution.

 

Renesas Technology Test Strategy: Compressed Deterministic Pattern Test

Renesas Technology developed compressed deterministic pattern test (CDPT) to resolve the problem of test cost while ensuring test quality. The design restriction is equal to Scan and the pattern is compressed from 10X to 100X.

Overhead issues are also managed with an embedded deterministic test (EDT) circuit added to the Scan circuit. As a result of this approach, Renesas Technology was able to extend its test methods. TestKompress was adopted as the standard CDPT tool.

Fig. 1 Case Study for High Compression. Tester capability was 32M steps. Test pattern size was 51.3M with FastScan. TestKompress generated 0.6M steps as the pattern. Test time was 0.12 from 10.2 seconds or more. Test coverage was 96.96%, same as FastScan coverage. Test data can be stored in the ATE memory. One-time loading was performed by TestKompress.

Three main technological capabilities further convinced Renesas Technology to choose TestKompress. First, in large scale designs, high compression rate technology is a requirement. In a 10-million gate SoC, pattern size exceeds the ATE pattern limitation. With TestKompress, which has a 50X or higher compression capability, the pattern for a 10-million gate SoC can be loaded by the ATE without re-loading.

Second, modular TestKompress enables the user to add TestKompress logic on a block by block basis, eliminating potential routing issues. High compression at the top level would otherwise cause routing issues. In fact, TestKompress can be implemented with as few as one scan channel, significantly reducing top-level test signal routing.

Third, many potential delay faults exist in deep submicron processes; the ratio of the delay fault increases by 10X or more from 180nm to 130nm. Delay faults do not appear when a slow speed clock is employed. At-speed test is required, as it is based on internal PLL clock. TestKompress can perform the at-speed test with internal PLL clock by Named Capture Procedure.

Between April 2004 and December 2005, Renesas Technology successfully completed 50 tape-outs, manufactured 10 million chips and enjoyed compression rates of up to 85X using TestKompress. That's why Mentor Graphics TestKompress is the standard test solution for all mainstream designs at Renesas Technology.

Fig. 2. Result of modular EDT. Most wire shorts could be fixed using modular EDT. Layout capability can be improved for DFT using the modular method.

 
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