White Papers
Faster Time to Root Cause with Diagnosis-Driven Yield Analysis
This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software products.
Abstract: ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening a manufacturer’s profitability. Diagnosis-driven yield analysis is a methodology that leverages production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss prior to failure analysis. This methodology can reduce the root cause cycle time with 75-90%. The methodology can be expanded with DFM-aware yield analysis to help separate design and process related yield limiters.
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Optimizing Test to Enable Diagnosis-Driven Yield Analysis
Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during ATPG/DFT, what design data to archive, how to optimize your test program, how much data to collect, and what/how much diagnosis to perform. This white paper will address how to optimize the test environment in order to enable efficient diagnosis-driven yield analysis.
Defects and Defect Detection Industry Trends
This white paper describes the known common manufacturing defects and methods for detecting defects.
At design nodes smaller than 90 nm, manufacturing test challenges grow exponentially as compared to larger design nodes. At larger design nodes, manufacturing defects were typically a bridge or open that could be detected using a stuck-at tests. At smaller design nodes defects that effect at-speed performance are becoming more common and slow speed testing will not detect them.
Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be:
- Accurate
- With high resolution, and...
- Meaningful defect classifications
Significant improvements have been made in scan logic diagnosis algorithms. However, the defect classifications, accuracy, and resolution provided by diagnosis tools are, in general, insufficient for effective yield and failure analysis. Through layout information Tessent™ Diagnosis improvements all three items, becoming a powerful tool in the hands of the failure analysis and yield engineer.
Layout information enables Tessent Diagnosis to improve accuracy and resolution by 70% to 85% depending on the defect type and allows layout-validated defect types. More meaningful reporting for example on the polygon level prepares the diagnosis results for direct use by engineers.
In the appendix, we discuss layout-aware flows and file formats, and summarize Tessent Diagnosis’ true layout-aware approach.