White Papers

This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.

Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital blocks, and diminishing supply voltages. Both this complexity and the need for energy efficiency in portable and wireless IC designs are increasing the level of concern over power use and power control during test.

Attempts to manage power are being made at both the design and functional levels. Modular partitioning, power-domain gating, and clock gating are all techniques to manage dynamic and static power dissipation at the system level. When planning for power-aware design-for-test (DFT) and creating production test patterns, these design techniques also should be considered and, in some cases leveraged, to manage power during test.

Using the techniques outlined in the paper, scan shift switching can typically be reduced from 50% (normal level as even distribution on 1s and 0s) to 25% with minimal impact on test time. Capture switching activity can also be reduced by a significant amount, but the switching activity reduction as well as the impact on test time is highly design dependent. Designs with well-structured data paths and hierarchical, fine grained clock gating schemes can achieve capture switching activity of less than 10% with no coverage loss.

This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices.

To achieve today's quality and defect-per-million (DPM) goals, high-quality testing must achieve very high defect coverage. Testing today typically consists of generating test patterns based on multiple fault models that emulate manufacturing defects. Commonly used fault models include stuck-at, bridging and transition.

With each step down in process node size, there are new defects introduced into the manufacturing process. Many of these defects may be detected via the existing fault models and test pattern generation methods, but there are cases where in order to maximize coverage, a new fault model needs to be created.

Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time.

3D chips connected via interposers are expected to go into production in 2011 or 2012 at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die.

Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TestKompress has now been used in roughly one billion production chips. There has been a surge of compression techniques promoted in the industry since TestKompress was released in 2003. So, why has TestKompress become the standard approach in industry? This paper will try to explain the technology behind the various compression techniques and their robustness in the presence of Xs, false and multi cycle paths, low pin access, and other design factors.

The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins.  DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins.  Low Pin Count Test (LPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying LPCT, devices can be easily tested on structural DFT testers at dramatically reduced costs while meeting the low pin count requirements of device and design flow.  Combining LPCT with test compression further extends the test capabilities to allow application of all necessary fault models using low-cost testers that are seriously pin-limited. The techniques described here enable gains in test coverage with less application time and minimal effects on design and test overhead.