Technical Publications
Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be accurate, with high resolution and, meaningful defect classifications.
Significant improvements have been made in scan logic diagnosis algorithms. However, the defect classifications, accuracy, and resolution provided by diagnosis tools are, in general, insufficient for effective yield and failure analysis. Through layout information YieldAssist improves all three items, becoming a powerful tool in the hands of the failure analysis and yield engineer.
Layout information enables YieldAssist to improve accuracy and resolution by 70% to 85% depending on the defect type and allows layout-validated defect types. More meaningful reporting for example on the polygon level prepares the diagnosis results for direct use by engineers. In the appendix, we discuss layout-aware flows and file formats, and summarize YieldAssist’s true layout-aware approach.
Beyond Pass/Fail Testing: Using Failure Data from Manufacturing Test for Yield
As feature sizes shrink, the number of non-visual defects increases. At the same time, traditional methods for defect identification and yield learning are becoming less effective. Scan design has been the enabling technology for high quality manufacturing test for many years. Now with advanced diagnostics capabilities, a company's investment in scan design can now be used for yield learning and yield monitoring. If properly leveraged, scan-based test and diagnostics can play an important role in yield learning and yield monitoring for nanometer design.
Achieving High-Quality Test for ARM Artisan Memories
High quality testing of today's nanometer designs is increasingly more essential - and more complicated. One aspect of this, memory testing, is becoming more of a concern as well. Not only is the amount of memory increasing, but the diversity of memories in an SoC design is also growing. Embedded memory has a wide range of uses, speeds, sizes, and configurations. Because memories are such dense structures, they are more susceptible to defects than logic. Understanding and detecting these defects is the key to developing a good memory test plan. Memory IP suppliers, such as ARM®, recommend a set of algorithms for testing their memories based on architecture and implementation. The partnership between Mentor Graphics® and ARM enables joint customers to easily develop high quality test for memories, which is a foundational part of any test strategy. This paper discusses both the memory testing algorithms recommended by ARM and how MBISTArchitect™ can be used for thorough testing, diagnosis and repair of these memories.
Logic BIST Application and Usage
There are several applications where logic BIST is an important test approach and valuable methodology. This paper describes the most common use of logic BIST as supported by LBISTArchitect and common tradeoffs on when and where to apply logic BIST.
Combining Compression with Fewer Pins Dramatically Saves I/O during Multi-Site Test
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Reduced pin count testing (RPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying RPCT, devices can be easily tested on structural DFT testers at a cost of about $200/pin compared to the high-end functional testers that cost almost $8,000-10,000/pin.
By combining RPCT with test compression, we have extended the capabilities of multi-site testing to allow application of at-speed test patterns using low-cost testers that are seriously pin-limited. We were able to free up device I/O by 90%. The method proposed here enables gains in test coverage with less application time and minimal effects on design and test overhead. It can be used in multi-site test, with simpler fixturing.
High Quality Test Solutions for Secure Applications
Designs for secure applications such as smart cards and those used in the defense industry require security to ensure sensitive data is inaccessible to outside agents. Conversely, scan chains have been used for decades to improve access to internal logic for automatic tester equipment (ATE) so that devices can be tested efficiently and quickly. This conflict in requirements has forced many designers of secure applications to use logic BIST and sacrifice test quality in some cases, or perform deterministic scan test in very costly secure test environments. Contributing to these challenges are the ever-increasing requirements for high quality test and additional test requirements for fabrication processes at smaller geometries. In this paper, we will explore the techniques currently in use for testing devices designed for secure application and review the benefits and challenges of each available solution.
The Next Generation of Embedded Test Compression: TestKompress(r) Xpress Compactor
The new embedded compression hardware used by TestKompress called Xpress provides significant improvement in compression of test data and test application time for designs with large number of Xs. This paper provides an overview of test quality and cost requirements of nanometer designs as well as the impact of X sources on test quality. A high-level description of the Xpress hardware is followed by benchmark results from industrial designs of Mentor's customer partners.
YieldAssist and Its Successful Industrial Applications
Yield Improvement, Verified Flow, Accuracy, Layout Aware and Volume Diagnosis
Feature-related defects are becoming more prevalent than particle-driven defects in nanometer designs. The process and design variances require checks for the design-for-manufacturing (DFM) issues in order to achieve a high yield. Scan diagnostics targeted for the nanometer designs can provide quick, accurate and reliable failure information from the production environment. The sorted, fault classified and physically linked scan diagnosis results can, in turn, provide the guides for DFM checks. High volume diagnosis provides data to yield management system for statistical analysis. YieldAssist, Mentor's scan diagnosis solution has been adopted by many customers to meet these goals. This paper explains the technology behind it, discusses its applications and shows the results.
The Robustness of Various Test Compression Techniques
Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TestKompress has now been used in roughly one billion production chips. There has been a surge of compression techniques promoted in the industry since TestKompress was released in 2003. So, why has TestKompress become the standard approach in industry? This paper will try to explain the technology behind the various compression techniques and their robustness in the presence of Xs, false and multi cycle paths, low pin access, and other design factors.
At-Speed and Advanced Fault Models for Achieving High Quality Test
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.
Design Flows Using TestKompress
Different embedded compression products and technologies have been tried and discarded as the marketplace selects the solution that best meets all the requirements. Users have determined that a successful embedded compression tool is required to:
- Maintain high test quality (i.e. support all fault types)
- Achieve high test compression of both test time and test data (up to 100X)
- Have little or no impact on the functional design
- Add minimal area
- Easily fit into the design flow
As evidenced by its widespread industry adoption, TestKompress has met or exceeded all of these requirements while requiring as few as a single scan channel and offering diagnostics directly from compressed patterns. While Design-For-Test (DFT) groups are typically most concerned with high test quality and Operations Test is focused on reducing test time and data, design teams are most concerned with how any tool or methodology will impact the design and how it will fit into their existing design flow. This paper will describe the various design flows that TestKompress supports for the generation, insertion and synthesis of its embedded compression logic. The advantages of each flow are discussed so that the designer can decide which best fits into his or her existing design flow.