Technical Publications
Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins.
Low pin count testing (LPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying LPCT, devices can be easily tested on structural DFT testers at dramatically reduced costs while meeting the low pin count requirements of device and design flow. Combining LPCT with test compression further extends the test capabilities to allow application of all necessary fault models using low-cost testers that are seriously pin-limited. The techniques described here enable gains in test coverage with less application time and minimal effects on design and test overhead.
Comprehensive Hierarchical DFT for System-On-chip Devices, Tessent SoCScan Technology Backgrounder
Designers of large System-On-Chip (SOC) chips have increasingly adopted hierarchical design practices in order to more efficiently complete work at the core level and simplify integration at the SOC level. Design-For-Test tasks such as test insertion, pattern generation and SOC integration benefit from the same hierarchical approach. The Tessent SoCScan toolset automates the work and flow required to insert test logic, isolate cores, integrate cores into the SOC and reuse core level patterns at the SOC level providing all the benefits of a hierarchical DFT flow.
Why Use Embedded Test for High-Speed Serial I/Os?
One of the most notable consequences of the semiconductor industry moving to deeper nanoscale technology nodes is the significant growth in both the number and densities of embedded memories. Designs have migrated from containing a handful of memories to containing hundreds and in some cases over a thousand memories of all types. This explosion in embedded memories is driving the need for rethinking the manufacturing test strategy for these designs [1]. In particular, embedded memories now represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must now incorporate some form of repair methodology in order to achieve profitable yield levels. Formulating a repair methodology often requires combining IP from memory providers, automation from DFT providers, and data from foundries. This often represents a significant challenge as not only are there several combinations and choices to consider, but more importantly, there is generally very little information on how to best make these choices. This paper attempts to address this challenge by explaining the memory repair process along with all of its components and choices as well as by providing repair related information on popular memory IP vendors and foundries.
Faster Time to Root Cause with Diagnosis-Driven Yield Analysis
This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent™ Diagnosis and Tessent YieldInsight™ software products.
Abstract ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening a manufacturer’s profitability. Diagnosis-driven yield analysis is a methodology that leverages production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss prior to failure analysis. This methodology can reduce the root cause cycle time with 75-90%.
Memory Repair Primer: A guide
One of the most notable consequences of the semiconductor industry moving to deeper nanoscale technology nodes is the significant growth in both the number and densities of embedded memories. Designs have migrated from containing a handful of memories to containing hundreds and in some cases over a thousand memories of all types. This explosion in embedded memories is driving the need for rethinking the manufacturing test strategy for these designs [1]. In particular, embedded memories now represent in most cases a die’s largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must now incorporate some form of repair methodology in order to achieve profitable yield levels. Formulating a repair methodology often requires combining IP from memory providers, automation from DFT providers, and data from foundries. This often represents a significant challenge as not only are there several combinations and choices to consider, but more importantly, there is generally very little information on how to best make these choices. This document attempts to address this challenge by explaining the memory repair process along with all of its components and choices as well as by providing repair related information on popular memory IP vendors and foundries.
BIST Techniques for Delay and Jitter
As on-chip delays-of-interest range from nanoseconds down to picoseconds, off-chip delay measurement techniques are limited by fundamental properties of signal access paths, such as noise and impedance variation. This tutorial discusses most of the papers published in the last 10 years that provide silicon results for on-chip measurement techniques, and a few that include only simulated results, to discover the most promising directions for characterization and production testing of IC signal timing parameters such as delay, jitter, and pulse width.
Noise Insensitive Digital BIST
PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, subpicosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.
Layout-Aware Diagnosis
Scan logic diagnosis is a powerful tool to help failure analysis engineers determine the root cause of a failing die. Yield engineers, on the other hand, are interested in statistical analysis of volumes of high-quality diagnosis results to determine yield limiters. To be of value for both engineers, a diagnosis tool needs to be:
- Accurate
- With high resolution, and...
- Meaningful defect classifications
Significant improvements have been made in scan logic diagnosis algorithms. However, the defect classifications, accuracy, and resolution provided by diagnosis tools are, in general, insufficient for effective yield and failure analysis. Through layout information Tessent™ Diagnosis improvements all three items, becoming a powerful tool in the hands of the failure analysis and yield engineer.
Layout information enables Tessent Diagnosis to improve accuracy and resolution by 70% to 85% depending on the defect type and allows layout-validated defect types. More meaningful reporting for example on the polygon level prepares the diagnosis results for direct use by engineers.
In the appendix, we discuss layout-aware flows and file formats, and summarize Tessent Diagnosis’ true layout-aware approach.
At-Speed and Advanced Fault Models for Achieving High Quality Test
With the increasing clock speeds and the decreasing feature sizes found in today's nanometer designs, at-speed testing is a requirement to achieve high quality test results. In addition, new advanced fault models are also available to improve defect detection and lower DPM rates. Advanced at-speed test capabilities and some new fault models are described in this paper.
High Quality Test Solutions for Secure Applications
Designs for secure applications such as smart cards and those used in the defense industry require security to ensure sensitive data is inaccessible to outside agents. Conversely, scan chains have been used for decades to improve access to internal logic for automatic tester equipment (ATE) so that devices can be tested efficiently and quickly. This conflict in requirements has forced many designers of secure applications to use logic BIST and sacrifice test quality in some cases, or perform deterministic scan test in very costly secure test environments. Contributing to these challenges are the ever-increasing requirements for high quality test and additional test requirements for fabrication processes at smaller geometries. In this paper, we will explore the techniques currently in use for testing devices designed for secure application and review the benefits and challenges of each available solution.
The Robustness of Various Test Compression Techniques
Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TestKompress has now been used in roughly one billion production chips. There has been a surge of compression techniques promoted in the industry since TestKompress was released in 2003. So, why has TestKompress become the standard approach in industry? This paper will try to explain the technology behind the various compression techniques and their robustness in the presence of Xs, false and multi cycle paths, low pin access, and other design factors.