Low Pin Count Test White Papers
Reduce Routing Congestion & Test Cost with Low Pin Count Compression
Applying deterministic scan patterns with a smaller pin interface addresses several test cost and quality challenges such as requirements on chip level routing, tester and chip pin limitations, multi-site testing, etc. For this to be valuable, the key is maintaining the high quality and test coverage of scan patterns across all needed fault models. Tessent™ TestKompress® is the industry’s leading solution that uniquely enables high coverage and high compression while minimizing the tester interface to as few as 1 scan channel.Requested Whitepaper
Combining Low Pin Count Test with Scan Compression Dramatically Reduces Test Interface and Cost
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand…
The manufacturing test process for ICs is increasing in cost and effort to keep up with rigorous quality standards, complexity of newer designs and process nodes, narrower time-to-market windows, and demand to reduce test pins. DFT engineers are using advanced fault models to improve test quality. However, increasing test time and volume, which translates into increased cost, is forcing many companies to apply the necessary tests in fewer test cycles and, if possible, with fewer pins. Low Pin Count Test (LPCT) is a technique to reduce the cost of test by minimizing the pin requirements of a device when tested on an ATE. By applying LPCT, devices can be easily tested on structural DFT testers at dramatically reduced costs while meeting the low pin count requirements of device and design flow. Combining LPCT with test compression further extends the test capabilities to allow application of all necessary fault models using low-cost testers that are seriously pin-limited. The techniques described here enable gains in test coverage with less application time and minimal effects on design and test overhead.
Running Scan Test On Three Pins: Yes We Can!
Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three…
Imagers are pretty little objects nowadays, their size is always shrinking and having only three standard digital pins available on their package is a most common thing. Looking back in 2006, only three years ago, people asked for a solution to run industrial structural test on such complex devices could though only reply “impossible” or “Do It Yourself”. STMicroelectronics did not escape the rule. An internal development and a partnered development were thus successively launched to address this issue.
This article proposes to examine all the why and how of these developments along with the good results obtained during that time, in terms of test cost improvement, area overhead in silicon, design flow updates and industrialization process. Getting all sensors designed today equipped and test data volume (and time) improvements in the range of 25X to 30X just took that three years time. Now that the solution is industrially available, it’s also time to share and look at the future of industrial scan test on three pins… Reprinted with permission of IEEE and STMicrolelctronics
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