White Papers
Why Use Embedded Test for High-Speed Serial I/O
Serializer/deserializer (SerDes) transceivers are being implemented in ICs today to support standards such as PCI-Express, XAUI, SATA, HyperTransport, Fibre Channel, Rapid I/O, Infiniband, SONET, Ethernet, HDMI, and USB. Mainstream data rates for SerDes range from 2.5 Gbps (Gigabits per second) to over 10 Gbps. Performing manufacturing test and characterization on these transceivers typically require very expensive test equipment and a lot of time. Utilizing embedded test for SerDes enables any ATE or desktop test system to test and verify these transceivers. Tessent SerdesTest provides results in less than half a second.
BIST Techniques for Delay and Jitter
As on-chip delays-of-interest range from nanoseconds down to picoseconds, off-chip delay measurement techniques are limited by fundamental properties of signal access paths, such as noise and impedance variation. This tutorial discusses most of the papers published in the last 10 years that provide silicon results for on-chip measurement techniques, and a few that include only simulated results, to discover the most promising directions for characterization and production testing of IC signal timing parameters such as delay, jitter, and pulse width.
Noise Insensitive Digital BIST
PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, phase error, output frequency, duty cycle, lock time, and lock range. Two techniques for cancelling random and systematic noise are also described. The multi-GHz range, subpicosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.