White Papers
Ready for 3D-IC
This technical presentation describes the challenges and Mentor's solutions for verifying and testing IC designs targeted for 3D packages, such as stacked die using TSVs or multi-die packages using silicon interposers.
Using Tessent Low Power Test to Manage Switching Activity
Today’s advanced integrated circuit (IC) designs are increasing in complexity, with their seemingly endless progression to smaller geometries, ever increasing integration between analog and digital blocks, and diminishing supply voltages. Both this complexity and the need for energy efficiency in portable and wireless IC designs are increasing the level of concern over power use and power control during test.
Attempts to manage power are being made at both the design and functional levels. Modular partitioning, power-domain gating, and clock gating are all techniques to manage dynamic and static power dissipation at the system level. When planning for power-aware design-for-test (DFT) and creating production test patterns, these design techniques also should be considered and, in some cases leveraged, to manage power during test.
Using the techniques outlined in the paper, scan shift switching can typically be reduced from 50% (normal level as even distribution on 1s and 0s) to 25% with minimal impact on test time. Capture switching activity can also be reduced by a significant amount, but the switching activity reduction as well as the impact on test time is highly design dependent. Designs with well-structured data paths and hierarchical, fine grained clock gating schemes can achieve capture switching activity of less than 10% with no coverage loss.
High Quality Test of ARM® Cortex™-A15 Processor Using Tessent® TestKompress®
This white paper provides a high level overview of the Mentor reference flow for ARM architecture.
Customers are integrating single or multiple ARM(r) Cortex(tm)-A15 processors into their SoC designs in order to take advantage of this industry-leading IP. In order to perform manufacturing test for the SoC, a test strategy needs to be adopted and the corresponding DFT implemented to achieve that test strategy. Traditionally, it has been up to the design-for-test (DFT) engineer to understand the test strategy and implement the DFT associated with it.
With the introduction of this jointly developed Mentor reference flow for ARM architecture, DFT engineers now have a guide so they can effectively and efficiently test designs that include the ARM Cortex-A15 processor.
User Defined Fault Models
This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices.
To achieve today's quality and defect-per-million (DPM) goals, high-quality testing must achieve very high defect coverage. Testing today typically consists of generating test patterns based on multiple fault models that emulate manufacturing defects. Commonly used fault models include stuck-at, bridging and transition.
With each step down in process node size, there are new defects introduced into the manufacturing process. Many of these defects may be detected via the existing fault models and test pattern generation methods, but there are cases where in order to maximize coverage, a new fault model needs to be created.
3D-IC Testing with the Mentor Graphics Tessent Platform
Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore's Law. Current integration and interconnect methods include wirebond and flip-chip and have been in production for some time.
3D chips connected via interposers are expected to go into production in 2011 or 2012 at Xilinx, Samsung, IBM, and Sematech [1]. Interposers are providing the logical first step to industrialization of 3D based on through-silicon vias (TSV)s. The next generation of 3D integration incorporates TSV technology as the primary method of interconnect between the die.
Optimizing Test to Enable Diagnosis-Driven Yield Analysis
Using diagnosis-driven yield analysis, companies have decreased their time to yield, managed manufacturing excursions and recovered yield caused by systematic defects. Dramatic time savings and yield gains have been proven using these methods. Companies must plan ahead to advantage of diagnosis-driven yield analysis. The planning needs to include how and what patterns to generate during ATPG/DFT, what design data to archive, how to optimize your test program, how much data to collect, and what/how much diagnosis to perform. This white paper will address how to optimize the test environment in order to enable efficient diagnosis-driven yield analysis.
Defects and Defect Detection Industry Trends
This white paper describes the known common manufacturing defects and methods for detecting defects.
At design nodes smaller than 90 nm, manufacturing test challenges grow exponentially as compared to larger design nodes. At larger design nodes, manufacturing defects were typically a bridge or open that could be detected using a stuck-at tests. At smaller design nodes defects that effect at-speed performance are becoming more common and slow speed testing will not detect them.
Memory Test and Repair Solution for ARM Processor Cores
Many large systems-on-chip (SOC) designs today incorporate several third-party IP cores that cover a wide range of functionality. These cores often consist of high-performance embedded processors such as those available from ARM®. Highly optimized architectures and carefully tuned timing paths are required to achieve ever-increasing performance levels in these processors. Integrating design-for-test capabilities such as memory built-in self-test (BIST) and self-repair capabilities into these cores can affect performance levels because logic typically has to be inserted into functional paths.
Why Use Embedded Test for High-Speed Serial I/O
Serializer/deserializer (SerDes) transceivers are being implemented in ICs today to support standards such as PCI-Express, XAUI, SATA, HyperTransport, Fibre Channel, Rapid I/O, Infiniband, SONET, Ethernet, HDMI, and USB. Mainstream data rates for SerDes range from 2.5 Gbps (Gigabits per second) to over 10 Gbps. Performing manufacturing test and characterization on these transceivers typically require very expensive test equipment and a lot of time. Utilizing embedded test for SerDes enables any ATE or desktop test system to test and verify these transceivers. Tessent SerdesTest provides results in less than half a second.
The Robustness of Various Test Compression Techniques
Larger designs and the growing population of non-stuck defects have led many companies to adopt test compression techniques. In fact, the Embedded Deterministic Test (EDT) technology within TestKompress has now been used in roughly one billion production chips. There has been a surge of compression techniques promoted in the industry since TestKompress was released in 2003. So, why has TestKompress become the standard approach in industry? This paper will try to explain the technology behind the various compression techniques and their robustness in the presence of Xs, false and multi cycle paths, low pin access, and other design factors.
Faster Time to Root Cause with Diagnosis-Driven Yield Analysis
This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software products.
Abstract: ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening a manufacturer’s profitability. Diagnosis-driven yield analysis is a methodology that leverages production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss prior to failure analysis. This methodology can reduce the root cause cycle time with 75-90%. The methodology can be expanded with DFM-aware yield analysis to help separate design and process related yield limiters.