Analog Modeling - Part 6

In Part 5 of this series we used the mathematical descriptions of the thermal and electrical properties of an incandescent lamp to create the architecture of a VHDL-AMS-based simulation model. Now it’s time to finish the model, and this blog series, by creating a VHDL-AMS entity for the lamp model.

As I mentioned in Part 5, the VHDL-AMS entity defines how a model connects to other elements in a system, and the properties users can adjust to characterize the model’s behavior. In VHDL-AMS, model connections are called “ports”, and user defined properties are called “generics”.

VHDL-AMS supports multiple port types. Since we’re modeling the analog behavior of the lamp, we’ll use terminal ports, which represent analog connections in VHDL-AMS. Terminals also have a defined nature relating to the technology of the model. For our lamp, we’ll attach electrical natures to the terminals.

In general, VHDL-AMS generics are simply user defined constants. Similar to assigning a nature to a terminal, a generic must be assigned a type. For analog modeling, common types for generics include “real” and “integer”. Types can also be technology specific like “temperature” or “resistance”.  With this brief introduction to the main elements in a VHDL-AMS entity, let’s see what we need to define for the lamp model.

The architecture for the lamp model contains a single branch quantity statement:

            quantity v across i through p1 to p2;

Anytime a VHDL-AMS architecture contains a branch quantity statement, there needs to be a corresponding port definition in the entity. Here the model’s voltage (v) and current (i) are defined in relation to p1 and p2. In this case, p1 and p2 represent terminals for the branch, and therefore terminals for the model. Since this is the only branch quantity in the model, p1 and p2 are the only model terminals. Using VHDL-AMS syntax, the port statement in the entity looks like this:

            port (terminal p1,  p2 : electrical);

Next, we need to review the architecture and create a list of constants to be declared and defined. To support the lamp model’s architecture, the following constants need to be defined in the entity:

            alpha, cth, ke, r_cold, rth, temp_amp, temp_cold

Using VHDL-AMS syntax, the generic statement in the entity looks like this:

            generic (

                        alpha : real  := 0.0045;

                        cth : real  := 0.25e-3;

                        ke : real := 0.85e-12;

                        r_cold : resistance := 0.2;

                        rth : real := 400.0;

                        temp_amb : temperature := 27.0;

                        temp_cold : temperature := 27.0);

Note that all of these constants are assigned default values. While default values are not required, it’s good practice unless you want to force users to assign a value prior to simulation. With the generics and ports defined, it’s time to complete the entity:

            Library IEEE;

            Use IEEE.electrical_systems.all;

            Entity lamp is

                   generic (

                                    alpha : real  := 0.0045;

                                    cth : real  := 0.25e-3;

                                    ke : real := 0.85e-12;

                                    r_cold : resistance := 0.2;

                                    rth : real := 400.0;

                                    temp_amb : temperature := 27.0;

                                    temp_cold : temperature := 27.0);

                   port (terminal p1,  p2 : electrical);

            end entity lamp;

The first two statements simply access an IEEE standard VHDL-AMS library that tells the model what an electrical nature for the terminals means. We use the “entity lamp is” statement to mark the start of the entity, simply copy our generic and port statements into the entity, and then use the “end entity lamp” statement to finish.

And that’s it. If we combine the entity above with the architecture in Part 5, we have a complete model for an incandescent lamp. Although this is a simple analog model, the general development process outlined in Part 2 applies to analog models of any complexity. Next time you need to model an analog device, try using this process as a model development roadmap.