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Partitioning & Testing of Firmware & Digital Hardware, Interface Compliance, & Performance Validation

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Overview

This webinar demonstrates partitioning and testing of firmware and digital hardware, interface compliance, and performance validation.

It extends the architectural platform to include architecture, timing and power characteristics. It takes an automated generative flow from the verified UML / SysML system models into a hardware-aware virtual platform that includes:

  • A hardware-aware virtual platform that includes an instruction-accurate ARM processor core
  • Custom hardware co-processors
  • Analog sensing and delivery subsystems
  • Parametric physiological models

The ability to make HW/SW tradeoffs is accelerated by the use of model compilation that allows the exact same executable system-level model to be realized as either embedded C++ or SystemC hardware models. For complex medical devices, this architectural virtual system reduces the need for expensive detailed physical prototypes.

What You Will Learn

  • Methodology for reducing time to market & increasing design robustness
  • Specific solutions to address design, verification & test challenges
  • A flow that supports tying requirements from specification through derived design and verification artifacts
  • A flow that supports early modeling of analog, mixed signal and physiological aspects of a system
  • A flow that supports early virtual system integration at the algorithm / functional level
  • A flow that supports generation of C, C++, and/or SystemC from UML / SysML executable models
  • A flow that supports early virtual system integration at the target language code / firmware level
  • A flow that supports comprehensive virtual system verification and validation including test harnesses, application software, firmware, digital hardware, analog hardware, mechanical and physiological elements

About the Presenter

Presenter Image John Vargas

John Vargas has more than two decades of experience in electrical, software and systems engineering with a long track record of creating innovative products and developing next-generation processes to speed up product design cycles. He has worked in the computer, automotive, aerospace, and medical industries performing both research and new product development. Vargas currently focuses on helping key customers improve their processes by assessing their total system needs and applying Mentor's leading-edge technology solutions to resolve their challenges.

Who Should View

  • VP/Director of Systems, HW, SW & Test groups
  • Managers of HW, SW, & Test groups
  • Project Managers tasked with reducing schedules while maintaining product quality
  • System engineers responsible for defining complex functional requirements
  • HW & SW architects responsible for selecting architectures & exploring tradeoffs between them
  • Engineering managers concerned about improving quality while reducing design-cycle time
  • System and electrical engineers responsible for electro-mechanical system specs, design and/or test
  • Manager/engineers involved in developing manufacturing test environments for complex multi-domain systems
  • Managers/engineers involved in analog, digital, or mixed-signal design
  • Embedded C/C++ software developers working on complex multi-domain systems

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