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Course Part Number: 249776
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Course Overview
Tessent™ Diagnosis will teach you to capitalize on the methods of defect discovery on failing devices in a production environment. Using the defect reports from Tessent Diagnosis you will be able to plan the analysis process in determining the root cause of failure, reducing time, and improving your hit rate. With the correlation between the Logical netlist and the Physical layout, you will have an indication of the most likely area where to begin the failure analysis.
Hands-on lab exercises will reinforce lecture and discussion topics all under the guidance of our industry expert instructors. You will be presented with many typical testing challenges as observed on the production floor and with the setup for high volume testing requirements.
You will learn how to
- Prepare Tessent™ TestKompress® and Tessent™ FastScan™ data for Tessent Diagnosis
- Prepare failure data from Automatic Test Equipment for Diagnostics
- Run Tessent Diagnosis
- Interpret diagnostics reports to determine the failure mode of the defect
- Link reported symptoms to clusters in physical layout view
- Prepare diagnostics to use Layout Marker notation
- Create enhanced patterns to enhance diagnostic resolution
- Prepare the automated diagnosis server to perform production volume diagnostics
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using Tessent Diagnosis software. Hands-on lab topics include:
- Generating test for use with Tessent Diagnosis
- Running Tessent Diagnosis to perform logic, chain, at-speed, and iterative diagnosis
- Reviewing reports from failing devices to understand and identify different failure modes
- Using Tessent Diagnosis to create enhanced patterns to increase the resolution of suspects
- Linking between diagnosis reports and netlist and/or layout views
- Setting up and running the automated diagnosis server to evaluate several fail logs for volume diagnostics
Prerequisites
- The student should have basic knowledge of Verilog and Unix operating system prior to attending this course
- An Introduction to Design-for-Test is advisable but not required