Advanced Verification Methodology with Questa
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Duration: 3 Days
Course Part Number: 229281
Pricing: 1500 USD
Description
This intensive, practical course is intended for Verification Engineers interested in the Advanced Verification Methodology (AVM) using SystemVerilog. While many engineers may have extensive verification experience this course will introduce the features of the AVM that allow the creation best-practice verification environments. Essential features of the AVM are the usage of Transaction Level Modelling (TLM) standard interfaces to allow reusable environments to be quickly constructed as well as the ability to use SystemVerilog Assertions (SVA) in the verification environment. Usage of SystemVerilog features like Object Oriented programming, Constrained Randomization and Functional Coverage are also discussed in the context of the AVM.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.
You will learn
- Transaction Level Modelling (TLM) Interfaces
- How the AVM uses TLM interfaces to build verification environments
- To create reusable verification IP (VIP)
- How to interface AVM testbenches to RTL designs
- The use of functional coverage to provide feedback
Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience using the AVM with software. Hands-on lab topics include:
- SystemVerilog Class refresher
- Creating producers and consumers with TLM interfaces
- Dynamic Elaboration of hierarchical verification components
- Using AVM analysis ports for self checking testbenches
- Managing messaging in an AVM testbench environment
- Interfacing AVM testbench environments with RTL design
- Creation of a complete coverage driven environment for an example design
Audience
Verification Engineers interested in using SystemVerilog for verification
Prerequisites
- SystemVerilog for Verification course or at least one year experience using SystemVerilog
- Some familiarity with concepts of verification such as constrained-random testing
- Some knowledge of object-oriented programming (OOP) is an advantage