VHDL for Digital System Design

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Duration: 3 Days
Course Part Number: 059080
Price: 1500 USD

Description

With the advance of semiconductor technology, the complexity of digital circuits has increased to a level that circuit designers cannot handle without the help of modern sophisticated Electronics Design Automation (EDA) tools. The design methodology for digital systems and digital integrated circuits has moved from the traditional logic design and schematic capture to the HDL (Hardware Description Language) and synthesis approach. VHDL is currently one of the two most popular HDL used by hardware designers.

This course covers the use of VHDL in high-level synthesis of digital system designs. The language VHDL as well as how it is used for describing and synthesizing various digital modules will be addressed. VHDL coding and synthesis issues on combinational and sequential modules including Finite State Machine will be discussed. In the hands-on sessions, the participants will not only learn the language through hands-on coding, synthesis and simulation of some practical designs, but they will also synthesize and test the designs with industrial software packages and FPGA devices.
The 5-day course comprises of lecture sessions on VHDL language, hands-on sessions on coding, synthesis and simulation and a fully-guided project and a semi-guided project, in which a complete digital system is coded in VHDL, simulated, synthesized and tested with FPGA devices. 

What You Will Learn

    • Concept of synthesis
    • Basics of VHDL language, including its use in synthesis of digital designs
    • VHDL coding style for synthesis
    • Simulation and verification of designs with VHDL
    • Industrial-standard design software for coding, synthesis and simulation
    • Hardware implementation of digital systems on FPGA devices 

      Who Should Attend

        
             
      • Designers and engineers who would like to use VHDL for digital system design or would like to gain knowledge on VDHL and high-level synthesis
      • Designers and engineers who have been working or involving in ASIC design, board-level system design or prototyping with FPGA/CPLD
      • Project managers and application/product/marketing engineers will gain knowledge on the current design methodology
       

      Prerequisite

      Digital system or logic design knowledge is preferable.

      Course Methodology

      This course is presented classroom style with hand-on practical sessions using industrial-standard software and hardware.

       

      Course Structure

      Day 1 
      • Introduction:
      (i) High-level Design Methodology
      (ii) VHDL History and Terminology
      • VHDL Fundamentals:
      (i) Data Types and Entity Declaration
      (ii) Structural, Dataflow and Behavioural Architectures
      (iii) Identifiers and Signal Declaration
      (iv) Operators and Signal Assignment
      (v) Process Statement, Wait Statement and Variable
      (vii) VHDL Attributes               
      • Testbench:
      (i) Concept and Modeling of Testbench
      (ii) System Tasks for Test Monitoring
      (iii) Testbench examples
      • Flow Control Constructs:
      (i) Conditional Constructs
      (ii) Looping Constructs
      (iii) Examples
      • FPGA Architectures and Features:
      (i) FPGA Architectures and Features
      (ii) FPGA Resources
      (iii) FPGA vs CPLD
      • Hands-on:
      (i) Coding of Digital Modules in VHDL
      (ii) Synthesis, Testbench Coding and Simulation
      (iii) FPGA implementation
                               

       Day 2

      • VHDL for Combinatorial Logic Circuits:
      (i) MUX, Decoders and Encoders
      (ii) Binary Comparator and Parity Checker
      (iii) Simple ALU, Tri-state Buffer and Bus
      • Package and Function:
      (i) Declaration and Usage
      (ii) Generic Parameter
      • Memories:
      (i) Modeling of ROM and RAM
      (ii) Memory Initialization
      • Coding Styles:
      (i) Operator Sharing
      (ii) Expression Grouping
      (iii) Common Expression
      (iv) Examples of if-else, case and loop constructs
      • IEEE Library:
      (i) Packages
      • Hands-on:
      (i) Coding, Synthesis and Simulation of Combinational Circuits
      (ii) RAM Modeling, Initialization and Simulation
      (iii) Function, Function Call and Generic Entity
      (iv) FPGA Implementation of Combinational Circuits 

       Day 3

      • VHDL for Sequential Logic Circuits:
      (i) Gated D Latch, Edge-triggered DFF, DFF with Reset
      (ii) Registers and Shift Registers
      (iii) Counters
      • Finite State Machine (FSM):
      (i) Moore Machine
      (ii) Mealy Machine
      (iii) Manual State Assignment
      (iv) One-Hot State Assignment
      • Speed Improvement Techniques:
      (i) Pipeline Design
      (ii) Retiming
      (iii) Synchronization Circuits
      • Coding Examples:
      (i) Sequence Detector
      (ii) Serial Multiplier
      (iii) Handshaking Controller
      (iv) Traffic Light Controller
      • Hands-on:
      (i) Coding, Synthesis and Simulation of Sequential Circuits
      (ii) Counter and Debouncing Circuit
      (iii) Signal vs Variable
      (iv) FPGA Implementation
      (v) Guided Design, VHDL coding and hardware implementation of a complete digital system
       
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