Scalable Verification

Mentor provides a complete set of advanced verification methodologies that:

  • Improve productivity, predictability and quality
  • Are based on standards (eliminate vendor lock-in and support any flow)
  • Incorporate the best technology
  • Span the entire SOC verification problem

OVM plus Questa in-depth

OVM for SystemVerilog

The Open Verification Methodology Enables Simulator, Verification IP, and Language Interoperability to Deliver on Promise of SystemVerilog.

OVM is based on the IEEE 1800 SystemVerilog standard and supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of Verification IP. The methodology is non-vendor specific and represents interoperability with multiple languages and simulators. OVM is fully open, and includes a robust class library and source code

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Questa

The Questa™ advanced verification environment from Mentor Graphics® combines high performance and high capacity with the most advanced verification capabilities in the industry.

Assertion-based verification (ABV), testbench automation, and coverage-driven verification (CDV) are supported by a self-contained assertion engine, an advanced constraint solver, and extensive functional coverage features. This complete set of advanced verification methodologies are enabled by a flexible architecture that is unrivaled in the area of language support.

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Veloce Emulator is one of the Hot 100 Products
of 2007

EDN Hot 100Veloce logic emulator was picked as one of the Hot 100 Products of 2007 by the editors of EDN magazine, an online and print publication serving design engineers and engineering managers worldwide. The list was published in the December 14, 2007 issue of the magazine.

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