Create mixed process systems-on-chip with higher density, lower power, and greater bandwidth—all without disrupting your existing design flows. Mentor tools provide full support for 2.5D (silicon interposer) and 3D (stacked die with TSVs) physical verification, extraction, simulation and testing.
Calibre for 3D-IC Sign Off
Calibre—the leading platform for IC physical verification, extraction, LVS and DFM—meets the needs of designers building 3D-IC products today, whether they are based on SiP, silicon interposers or stacked die with TSVs. Learn more
Tessent for 3D-IC Test
Mentor Graphics Tessent® product line provides solutions for unique IC test challenges with the migration to 3D-ICs using silicon interposers or through silicon vias (TSV). Learn more
3D-IC Design and Test Resources
3D IC Test
Technology Overview: 3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics... View Technology Overview
3D-IC System Verification Methodology: Solutions and Challenges
White Paper: Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates... View White Paper
View all 3D-IC Design and Test Resources: White Papers, Datasheets, Web Seminars, and more