Calibre for 3D-IC Sign Off
Calibre—the leading platform for IC physical verification, extraction, LVS and DFM—meets the needs of designers building 3D-IC products today, whether they are based on SiP, silicon interposers or stacked die with TSVs.
The Calibre solution integrates seamlessly with current design flows and design styles, providing the ability to verify the design of multi-die stacks based on separately verified die. Using these techniques, designers can create mixed process systems-on-chip with higher density, lower power, and greater bandwidth—all without disruption to their existing flows.
Support For Both 2.5D and 3D Packaging
The industry is converging on two basic configurations for stacked dies, one using TSVs for vertical chip-on-chip stacking, the other using side-by-side dies connected via silicon interposers. Regardless of the configuration, Calibre provides complete design verification including DRC, LVS, parasitic extraction (PEX) and simulation with maximum flexibility to mix die components manufactured with different processes or at different process nodes.
Seamless Integration of 3D Into Your Existing
Calibre supports DRC/LVS/PEX of individual dies separately, followed by verification of the packaging interfaces. Based on package information (die order, x/y position, rotation and orientation etc.) provided in a rule deck, Calibre performs all DRC and LVS checking of complete multi-die 2.5D-IC and 3D-IC systems, and also provides parasitics in the form of individual chip netlists and a 3D stack top level netlist for simulation. Calibre delivers these capabilities without breaking your current tool flow or requiring new data formats.
Evolution of Chip Packaging.
Stacked die using TSVs to make front-side to back-side connections and flip-chip microbumps to make inter-die connections.
Physical verification of 3D configurations includes checking alignment of pads on dies and substrates (interposers), as well as layout-to-schematic checking for proper connectivity across the entire stack.
Checking die alignment.
3D-IC Design and Test Resources
Technology Overview: 3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics... View Technology Overview
White Paper: Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates... View White Paper