Tessent for 3D-IC Test
Three-dimensional stacked integrated circuits (3D-ICs) are composed of multiple stacked die, and are viewed as critical in helping the semiconductor industry keep pace with Moore’s Law. Current integration and interconnect methods include wire bond and flip-chip and have been in production for some time.
The next generation of 3D integration incorporates through-silicon-via (TSV) technology as the primary method of interconnect between the die. The migration to 3D-ICs connected by TSVs presents three new test challenges to the industry:
- Managing the escape rate of defective die at wafer test to meet target post-packaging yield.
- Testing memory die stacked on logic die configurations.
- Testing logic stacked on logic die configurations.
The Tessent® silicon test and yield analysis solutions provide a comprehensive set of design-for-test (DFT) capabilities that address the known-good-die testing challenges. These include the industry-leading solutions for ATPG, compression, logic BIST, memory BIST, boundary scan, mixed-signal BIST and silicon learning.
Testing Stacked Memory-on-Logic
Using Tessent’ s integrated hierarchical test capabilities, high-quality tests can be implemented for stacked logic and memory die. Tessent MemoryBIST provides at-speed testing of stacked memory die with support for all popular DRAM protocols, including those supporting the common JEDEC WideIO interface standard. This allows memory BIST controllers in a logic die to handle a variety of memory die stacked on top for different product variations.
Tessent also supports at-speed testing of memory buses, which covers both bond wires and TSV interconnects. A shared-bus capability enables test of multiple memory die on the same interconnect.
Testing Stacked Logic-on-Logic
For logic-on-logic stacks, the Tessent hierarchical test capabilities are used to test the stacked die and the TSV interconnects. The ATPG and BIST tests that were generated for single die testing are reused, saving test development times. The patterns are re-sequenced as required to ensure correct pattern distribution and application across multiple die.
The Tessent hierarchical ATPG solution is used to test TSVs between logic die. These TSVs are assumed to exist between the boundaries of scan isolated cores on neighboring die. Test patterns are generated using the full package netlist where a gray box model is used for non-targeted die and/or cores.
By using a combination of hierarchical test architecture, high compression scan testing, and BIST technologies, the Mentor Graphics Tessent solution provides the highest quality and most economical 3D-IC testing available.
DFT insertion and automatic test pattern generation (ATPG) with high compression.
Built-in self-test for embedded memories.
Built-in self-test for logic.
Hierarchical scan insertion and clock control infrastructure for at-speed testing.
At-speed tests including transition, multiple detect transition, timing-aware, and critical path.
3D-IC Design and Test Resources
Technology Overview: 3D-IC technology has been getting a lot of attention in the press and at technical conferences. Whether the 3D-IC is built on Silicon Interposers or stacked die with Through Silicon Vias, Mentor Graphics... View Technology Overview
White Paper: Presents a verification methodology for 3D-ICs, including connectivity checking and parasitic extraction. Discusses new challenges and EDA tools to responds to those challenges. An example illustrates... View White Paper