Safety Critical Design
Mentor Graphics tools and services provide aerospace and defense organizations with approaches and processes that ensure global competitiveness and profitability as well as confidence in product safety.
Our rigorous development process and advanced ASIC and FPGA design tools can help you meet your objectives with no compromise in performance, safety, and security. Mentor can help you develop devices to meet DO-254 quality objectives and government standards for reliability, durability, and efficiency. Requirements driven development provides continuity from system specifications into the hardware flow, including hardware definition, RTL coding through verification and synthesis.
- Continuous requirements tracking throughout design and verification
- Efficient and compliant electronic hardware development and verification
- Repeatable design development flow for consistent-quality process
- Extensive control and reporting for project management
- Comprehensive documentation for projects and certification support
- Consulting, training and partners provide support
A high-assurance design process needs evidence that a design performs its intended function, as specified by the requirements. Mentor’s solution for efficient requirements management and traceability with ReqTracer, ensures that all requirements are met throughout the various development stages. Automating these capabilities allows you to validate that your implementation meets your requirements – ensuring product quality – in a cost-effective manner. Learn more about ReqTracer
- Link common applications such as DOORS, documents, or spreadsheets to detailed requirements within the hardware design and verification processes
- Choose granularity (level) of linking/tagging
- Perform “shadow” tagging of code so as not to modify code from previous design projects
- Meet DO-254 objectives for traceability in a simple, complete and automated manner
- Support change management processes with automatic detection of requirements changes and analysis of downstream impact
- Provide necessary documentation to support design reviews and audits
A text editor and a design development environment have significant differences. HDL Designer is a design development environment that helps our aerospace and defense customers create high assurance designs. It streamlines team design needs, automates code quality checking, and enables practical reuse supporting a repeatable methodology. HDL Designer offers configuration and version management capabilities and downstream integration ensures efficiency throughout design development. Learn more about HDL Designer
- Structure: Facilitates team design development to ensure consistency, repeatability, and ECO visibility with interfaces to all downstream tools.
- Process Control: Enforces coding style, supports file and version management, and maintains downstream results from simulation and synthesis.
- Code quality checking: Delivers a customizable RTL rule checker for linting and downstream code preparation.
- Visualization: Generates block diagrams and other design visualizations to help team members understand code structure and function.
- Documentation: Automatically generates documentation in HTML or Microsoft file formats. Dynamic updates or documents for reporting are easily created from the actual design files to ensure comprehensive and complete information.
- Configuration Management: Project-based design development ensures libraries, design files and related documents are contained for consistency and archiving.
- Review support: Supports preparing for, conducting, and documenting the design for project reviews.
HDL Designer is well suited for both ASIC and FPGA design development.
- Any Silicon
FPGA, Platform FPGA, Structured ASIC, ASIC, SOC, PLD,
- Any Vendor
Actel, Altera, Atmel, ChipExpress, Lattice, Xilinx, plus any ASIC foundry
- Any Language
VHDL, Verilog, SystemVerilog
- Any Flow
Integrated with all leading Simulation, Emulation and Formal solutions. Integrated with all commercial synthesis and P&R environments
Verifying that a device performs its intended function (and does not do anything unintended) is a crucial part of safety-critical design and required in your DO-254 flows. Mentor's industry-leading verification solutions support the most complex designs. Regardless of your current methodology, if you’re struggling with too much time spent in the lab or in verification, Mentor has solutions that can help improve your verification efficiency and end-product quality.
- ModelSim is the industry standard simulator in the mil-aero industry. You can run tests to simulate the behavior of your design early in the flow, catching bugs much earlier than you would if you waited for lab testing. ModelSim also includes code coverage, which you must run as part of elemental analysis if you are doing DAL A/B DO-254 projects. Learn more about ModelSim
- Questa builds on ModelSim’s strong simulation engine with a verification platform that provides modern verification methods for complex designs with multiple functions and concurrent behaviors. These methods include assertion-based design and assertion debugging, transaction-level stimulus, constrained random test generation, functional coverage and verification management (with automated links back to requirements). Learn more about Questa
- Questa tools bring formal verification methods to Mentor’s verification toolbox.
- Questa CDC provides a multi-level approach to identifying clock-domain crossing problems (which can have severe repercussions in hardware) early in the design cycle, where they can be debugged and fixed easily and cost-effectively. Learn more about Questa CDC
- Questa FV adds formal verification methods (e.g., model checking) to ensure exhaustive checking of interfaces, protocols, blocks, and safety-critical properties. Learn more about Questa FV
- FormalPro is the logic equivalence check tool used to verify logic netlists after synthesis and after routing. Netlist comparison back to the golden RTL code identifies defects and provides superior coverage to simulation while executing 100x faster than netlist simulation. FormalPro supports FPGA and ASIC flows. Learn more about netlist verification with FormalPro
- Seamless and Codelink: verifies HW/SW integration early in the design flow
- Certe Testbench Studio: automates and generates correct-by-construction OVM testbenches for advanced verification
- inFact: for automatically generating stimulus and executing intelligent testbenches to accelerate coverage closure
- SystemVision: enables modeling and analysis of mechatronic systems
A high priority for safety-critical and DO-254 flows is that the synthesis results are repeatable and generated with design assurance in mind. Precision Synthesis offers vendor-independent synthesis that ensures reliable design operation with safe FSM encoding, radiation-hardened device support, optimization control, integration with FormalPro for logical equivalency checking (LEC), and efficient design re-use for any FPGA device. Learn more about Precision Synthesis
Methodology Assessments and Consulting
If you are suffering from process inefficiencies – especially pertaining to verification methodology – and need to reduce the cost of DO-254 programs, Mentor experts can perform a Methodology Assessment of your design flow. They will provide a plan for safely and incrementally moving you towards a more modernized and efficient design flow with an eye toward DO-254 compliance.
- Reduced implementation cost of DO-254
- Use of DER approved methods
- Assurance of efficient deployment
- Risk mitigation of schedule slips or budget overruns
- Incremental improvements to your current methodology
- Proven process – used on over 50 projects
- Minimal disruption to your organization
- Recommendations targeted to your unique methodology, goals, and situation
- Can include implementation plan and ROI calculations
Mentor Consulting has extensive experience helping aerospace and military companies improve their methodology, achieve DO-254 compliance, accelerate success, and reduce risk, especially in new verification methods and testbench creation. We work directly with your design and verification teams to assess their verification requirements, architect a verification environment, help you implement a solution, and assist with planning and management. Our consultants are experts in SystemVerilog-based verification using Mentor's OVM methodology and advanced verification tool suite. Learn more about Mentor Consulting
Manage requirements in your FPGA and ASIC design flows. ReqTracer simplifies, automates and enables requirements traceability from specification of the hardware specification through HDL coding, implementation and validation.
Design creation/RTL Reuse and management environment for FPGA and ASIC design
ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.
Questa® Advanced Simulator
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
Questa® CDC Verification
The Questa Clock-Domain Crossing (CDC) Verification solution focuses on the interaction between these clock domains. Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.
Questa® Formal Verification
The Questa Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states.
Offers an intuitive environment with advanced synthesis optimizations to deliver superior quality of results, award-winning analysis to eliminate defects, and advanced operator inference to enable FPGA vendor-independent design.
FormalPro™ is the Mentor Graphics solution for gate-level regression testing of FPGAs and ASICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference.