Home Solutions DO-254 Verification and Validation Netlist Simulation/Analysis

Verification and Validation

DO-254 Lifecycle

Netlist Verification

This phase of verification usually requires re-simulating the RTL test suite on the netlist with back-annotated timing. Because this process can be quite time-consuming for large, complex devices, sometimes logical equivalency checking (LEC) can be used to augment this approach.

Using Logical Equivalency Checking to Verify the Netllist

A logic equivalency checking (LEC) verification process supports DO-254 compliance and helps reduce dependence on gate-level simulation for complex FPGA projects. In this video, DO-254 program manager Michelle... View Technology Overview

Simulating the Gate-Level Netlist with Timing

Gate-level simulation verifies the output of the synthesis and place & route tools and incorporates timing to bring the model closer to real implementation. It ensures that a device will perform precisely... View Technology Overview

Simplify netlist simulation and analysis

ModelSim or Questa for Netlist Simulation

Depending on your approach for RTL simulation, you can use the same method and test suite for netlist verification, i.e., ModelSim for traditional simulation and Questa for more advanced methods.

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FormalPro for Logical Equivalency Checking

FormalPro uses formal (mathematical) methods to compare one model to another, to determine if they are functionally equivalent. This is especially useful in DO-254 flows to verify that the synthesized (or placed-and-routed) netlist functions the same as the RTL. FormalPro can be used standalone or in a flow integrated with Precision Synthesis.

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