A few weeks ago, I introduced you to the start of a DFT Bootcamp series for those of us who wouldn’t know a DUT if we ran into one. Maybe you design ICs, but someone else adds the test circuitry to your layouts. All you know (grumble, grumble) is that those additions can change your design’s performance, increase the die size, and require additional verification. But even if you’re … Read More
Fabless/Foundry Ecosystem Solutions
IC design, verification, and test tools, resources, and expertise to help fabless designers create successful IC, IP, and SoC products manufactured at the world’s leading foundries.
Parasitic extraction is a pretty commonplace procedure these days in IC design. As geometries got smaller and more tightly packed, the resistance, capacitance and inductance of interconnects became significant enough to affect circuit performance. Accounting for these parasitic effects became a tapeout requirement, since they could cause signal noise and delays, as well as IR drop. EDA vendors stepped … Read More
Are you a calm person? Or are you easily irritated? We all have our limits and pressure points—just like a design layout. Certain geometries may have a high failure rate in production. Circuitry may fail when confronted with an ESD event. When your design passes verification, does that mean it’s all good? In theory, yes. In reality, everyone knows that the real world is a tough place for electronics. … Read More
I recently returned from my first-ever trip to Japan. While I was enthralled by its beauty and history, entertained by both traditional and avant-garde theatre, and enticed by new food opportunities, it was five minutes of television that caught my attention one day. Although I didn’t understand a word of the report, the problem was obvious—all over the region, vending machines were spontaneously … Read More
The 9th annual International Electrostatic Discharge Workshop (IEW) is being held May 4-7, 2015, at the Granlibakken Resort in Lake Tahoe, CA. The Call for Papers promises glimpses of “friendly but shy” bears and other wildlife at the conference site, located at 6,350 feet up in a mountain valley. Frankly, I prefer my bears to be decidedly shy, if that means they’ll be close enough … Read More
I have one opinion about electricity…if it’s invisible and it can kill you, it’s probably a good idea to avoid it. Now, some of my attitude is shaped by spending most of my childhood along the US Gulf Coast, where massive thunderstorms are an almost-daily occurrence during summer, and every little kid is taught to run for cover at the first rumble or flash. But that healthy fear means … Read More
Are you stressed out over the effects of stress in your IC designs? Relaaaax…help is here! A new publication on mechanical stress in ICs, co-edited by Valeriy Sukharev, Principal Engineer for Calibre R&D, has just been released by AIP Publishing. Stress-Induced Phenomena and Reliability in 3D Microelectronics includes papers from international workshops held in the U.S., Germany, and Japan. … Read More
In a SPIE.TV interview, Joseph Sawicki, Vice-President and General Manager of the Design to Silicon division of Mentor Graphics, explains the challenges of moving from design abstraction to physical implementation to a successful yield. “Design to silicon” is a complex process that continuously blends evolutionary trends, such as enhancements to 3D mask design and yield learning, with more … Read More
Design-style-based (systematic) defects are the major challenge to yield ramp at advanced process nodes, adding to the complexity of the basic process ramp. Because of its involvement in the design, manufacturing, and test, EDA is in a unique position to contribute toward the control, if not the solution, of this problem, through the use of automated pattern detection and analysis. Patterns can be useful … Read More
Failure analysis is a critical process in successful IC production. No matter how comprehensive the design rules are, no matter how thorough the verification strategies are, there will be chip failures in production. Understanding the cause of these failures is crucial to being able to implement design strategies and corrective technology to ensure the failures are eliminated in future designs. At its … Read More
If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation … Read More
No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!! And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is … Read More
The World Cup is here! Every four years, the culmination of hundreds of qualifying matches around the world brings the best national teams together for nearly a month of intense competition to determine the world champion football team (Sorry, USA, but it’s football everywhere else). New national uniforms are unveiled, shoe companies vie to sponsor the best players and teams with their most advanced … Read More
With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased … Read More
Remember learning your colors in kindergarten? Learning how to debug color assignment errors in multi-patterning can sometimes seem just as confusing. In Take Two of the Tech Talk videos on multi-patterning, David Abercrombie continues his discussion with Brian Bailey of Semiconductor Engineering about color assignment issues, and possible corrective actions. More often than not, a color assignment … Read More
- A "Crash" Course in Design-For-Test - the Rest of the Story
- Parasitic Extraction: It Doesn't Have to Hurt
- Testing Your Limits
- When Reliability Goes Up in Flames
- Friendly but Shy Bears, and other EOS/ESD Issues
- It's Electrifying!
- Manage Your Stress...Advice from the Experts
- Testing the Boundaries of Good Design
- Making the Impossible -- Dealing with Patterns Throughout the Design and Manufacturing Flow
- Failing to Succeed
- December, 2014
- November, 2014
- October, 2014
- September, 2014
- August, 2014
- July, 2014
- June, 2014
- May, 2014
- March, 2014
- February, 2014
- January, 2014
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- A Little Bit Here, A Little Bit There...Calibre Cluster Manager Reduces Turnaround Time
- TSMC OIP presentations now available!
- Can You Benefit from Cell-Aware Test?
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- How Do I?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- May, 2013
- April, 2013
- March, 2013
- May, 2009