Designing for power constraints is vital these days, whether you’re designing a battery operated device or a system that plugs into an outlet.
Mentor’s technologies allow you to address power at every stage in the design flow – from ESL through functional verification all the way to physical implementation.
Tackling power early in the design process is ideal, but balancing power with existing requirements of system functionality, performance, and manufacturability is closer to reality.
Mentor’s low power solutions were developed with partners who have successfully completed production designs so we have what it takes to do the job right. The Unified Power Format (UPF) provides the backbone to our technologies so engineers can define power based architectures, create power aware strategies, and verify low power designs throughout the TLM to GDSII flow.
Electronic System Level Design
A low power design flow that enables early, high-level exploration and tradeoffs is essential for success. Sensitivity analysis to architectural choices, software decisions, and impacts of the data sets must be all understood before RTL implementation begins. Adding implementation details leads to more accurate architectural models to verify the performance and power consumption of a system as it progresses through implementation. More on Electronic System Level Design
Power Aware Verification
Verification of correct design functionality of power requirements within the context of a power management scheme has traditionally been performed at the gate level, if at all. Defect rectification at this level is costly in terms of resource and design cycle. Today, design teams are moving to innovative techniques that enable power-aware verification at the RTL preserving traditional RTL design flows and block reusability. More on Power Aware Verification
IC Implementation
Meeting tight power constraints requires not just careful design planning, but a powerful physical implementation system with these key capabilities:
- Concurrent multi-corner, multi-mode (MCMM) optimizations for timing, power, and other design constraints across all your mode/corner scenarios
- Architectural support for advanced low power methodologies, such as multi-voltage, power gating, and DVFS
- Effective clock tree power optimization
On Demand: Low Power Webinar Series
This six part webinar series covers key aspects to the forces from a technology and market perspective that are driving designers towards better energy efficient designs and will show how to address power at every stage of your design process. View Low Power Series
A Guide to Power-Aware Memory Repair
White Paper: The number of embedded memories contained within an SoC continues to grow rapidly. This growth has driven the need for rethinking manufacturing test strategies as embedded memories represent in most cases... View White Paper
Low Power Resources
How Physical Implementation realizes Power Intent
Improving Circuit Reliability with Calibre PERC
News
- Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
- Mentor Graphics Provides Comprehensive Low Power Solution in TSMC Reference Flow 10.0
- Mentor Graphics Launches Precise-IP Vendor-independent IP Platform for FPGA Design
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions Limited for Design and Consulting Services
View all Low Power Resources: White Papers, Datasheets, Web Seminars, and more