Power Aware Verification
How Power Aware Simulation Ensures Working Designs
Mentor Graphic's power aware verification allows designers to functionally verify their power management techniques at the RTL -- reducing costs significantly in terms of effort and time.
Power aware verification works with normal RTL coding styles so designers don’t need to hand-instantiate gate-level retention cells for state data, and the power control network does not have to be intertwined tightly with the RTL functional specification. Thus, legacy RTL blocks are easily reused without modifying the RTL code, and new reusable blocks can be created independently of the power-aware environment they are targeted for.
What power aware verification does:
- Identifies all sequential elements inferred by the RTL design (registers, latches, and memories).
- Overlays the RTL design with the power control network.
- Pulls in the appropriate retention-cell model behavior.
- Dynamically modifies the behavior of the design to reflect the specified low power design intent in power down and up situations.
Power Aware Verification in Action
UPF extends the existing RTL with power-related functionality and bridges the gap between the power controller and the RTL extensions, making it easier to do functional verification at the RTL without embedding the power-related features into the golden RTL.
The design simulates normally after integrating the low power design specification with the RTL functional specification. Typically, the testbench, mimicking the software power management system, will exercise the power management block (PMB) through various system power states. The PMB implements those system states by switching power supplies, enabling or disabling isolation, gating clocks, and executing save and restore protocols.
The testbench can verify that the ‘awake’ portions of the design continue to operate properly while specific domains are powered down by the PMB. Assertions written using PSL or SVA can be employed to verify the correct sequence for power up/down, retention, and isolation. They can also be used to ensure proper functioning of the ‘awake’ portions of the design in various system power states.
When the power management strategy (based on test stimulus) determines that power domains need to be turned on, the PMB enables power to the power domains that were previously turned off and signals restoration of retained values for the sequential elements. Verification continues to ensure that the power domains come up in good known states and that the entire system can continue operating normally.
The net result is that power aware verification exposes power architecture and implementation functional bugs:
- Failure to retain sufficient state information to enable restoration of functionality when power is restored
- Dependency on output values
- Problems when interacting state machines in different power domains restore to states that create deadlock or live lock situation
- Improper sequencing of save and restore operations by the PMB
- Failure to reset a block upon power-on to a known good state for non-retentive blocks
- Activity in domains that are in a non-operational bias power state
Technical Tips
When a region of the design is powered down, it is often necessary to retain the state of the sequential elements so that the device can resume correct operation when power is restored. At the gate level, special retention flip-flops and latches are used that provide retention capability. When simulating at the RTL, behavioral power aware models must be created. These models mimic the power aware behavior of the gate level retention latches and flip-flops.
At the RTL, the designer can use the UPF map_retention_cell statement to map retention behavior onto specific regions or elements of the design. The simulator will then use the specified model to provide the retention behavior for the designated elements. This provides a mechanism to verify the correctness of the retention strategy without altering the RTL code.
More Information
Power Aware Verification
Products
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Questa® Advanced Simulator
The Questa® Advanced Simulator combines high performance and capacity simulation with unified advanced debug capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, PSL and UPF
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Questa Codelink
Codelink is an advanced debug toolset for functional verification of processor-based designs using your RTL or gate-level processor models. Codelink aids processor-driven verification by dramatically improving processor visibility and reducing the time it takes to debug failing processor-driven tests. It connects to existing processor signoff models without changing the design or simulation results.
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Questa® CDC Verification
The Questa Clock-Domain Crossing (CDC) Verification solution focuses on the interaction between these clock domains. Questa CDC addresses a number of critical verification issues that simply cannot be dealt with by simulation-based verification techniques.
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Questa® Formal Verification
The Questa Formal Verification tool complements simulation-based RTL design verification by analyzing all possible behaviors of the design to detect any reachable error states.
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FormalPro
FormalPro™ is the Mentor Graphics solution for gate-level regression testing of FPGAs and ASICs of 100,000 gates or more. FormalPro uses static formal verification techniques to prove that a design is functionally identical to its golden reference.
Datasheets
Contact Mentor Graphics
- Request Information or call toll free: 1-800-547-3000
Low Power Solutions
Electronic System Level
A new generation of tools from Mentor has recently debuted that delivers modeling fidelity and simulation performance at the early design exploration stage.
Power Aware Verification
Mentor’s power aware simulation gives designers the ability to functionally verify their power management techniques at the RTL, reducing costs significantly both in terms of effort and time.
IC Implementation
Mentor’s place and route solution, Olympus-SoC is UPF-compliant and handles a variety of low power design styles during placement, routing, and optimization.
Low Power Resources
How Physical Implementation realizes Power Intent
Improving Circuit Reliability with Calibre PERC
News
- Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
- Mentor Graphics Provides Comprehensive Low Power Solution in TSMC Reference Flow 10.0
- Mentor Graphics Launches Precise-IP Vendor-independent IP Platform for FPGA Design
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions Limited for Design and Consulting Services
View all Low Power Resources: White Papers, Datasheets, Web Seminars, and more