Automatic Place & Route for Low Power Styles
Mentor Graphic’s Olympus-SoC place and route solution is UPF-compliant and handles a variety of low power design styles during placement, routing, and optimization. Avoid inserting more risk into the design cycle by manually creating placement or routing “keep-out” areas, or trying to manually insert always-on buffers or isolation cells.
Olympus-SoC automates insertion of special cells, handles the routing of secondary power connections, and respects power domain boundaries and connectivity.
Save Power in your Clock Tree
Clocks are the single largest source of dynamic power usage, and clock tree synthesis and optimization is a good place to achieve significant power saving in physical design.
Low-power clock tree synthesis (CTS) strategies include lowering overall capacitance, improving clock gating coverage and minimizing switching activity. However, getting the best power results from CTS depends on the ability to synthesize the clocks for multiple corners and modes concurrently.
Mentor’s unique MCMM-based clock synthesis and optimization analyzes flop interactions to derive the skew balancing requirements across all corners concurrently. This results in vastly improved skew, area, and power in a single CTS run.
Closure Confidence with Concurrent MCMM Co-Optimization
A key dimension to low power implementation is managing the complexity inherent in today’s deep submicron designs. A typical low-power IC could have 3 or more power states—such as Standby, Active, and Sleep—plus a growing number of corners and modes, each of which can have conflicting requirements for timing, signal integrity (SI), manufacturability, and power.
MCMM makes a difference when taming power usage — because at advanced process nodes, lithography, process, and operational variability affect power in complex ways across different mode/corner scenarios. Variations in resistance due to uneven wire widths or CMP dishing can cause different results in one mode/corner scenario versus another.
Approximations, such as merging constraints from multiple process corners, can result in significant loss of accuracy, which makes closure difficult. With Mentor’s solution, all optimizations are concurrently applied to all mode/corner scenarios so you get the best quality of results while reducing guard-banding that lowers the bar on performance. That means you get lower power and higher performance, giving your ICs the edge over the competition.
Highest Tool Capacity for Large Designs
Olympus-SoC has the highest capacity of any place and route system so you can perform full-chip power, IR drop, and EM analysis on designs with 100 million gates or more, in flat or hierarchical modes. You are never forced to segment designs and manually merge them because of your tool’s limitations.
The Olympus-SoC place and route system reads the same UPF files you used in system design and verification, so power intent is carried through implementation. It supports advanced low power design techniques, including multiple voltage supply, power-shutoff, and voltage and frequency scaling.
The Olympus-SoC clock tree synthesis technology is the industry’s first multi-corner CTS engine. It produces very low power, highly optimized clock trees by analyzing flop interactions to derive the skew balancing requirements across all corners concurrently.
The Olympus-SoC router handles all the secondary power connections for retention flops and always-on buffers. It respects voltage island boundaries and changes routing topology to meet other design constraints. For example, the router detours around an island in order to buffer a signal integrity (SI) violation on a non-critical net, but allows critical nets to cross an island. To do this, it relies on constant updates on MCMM timing and RC to find the optimal solution for all key design constraints.
The router is variability-aware so it accounts for the manufacturing issues that affect power, especially leakage power. Without concurrent MCMM leakage and timing optimization, you may never be able to resolve conflicting needs across different mode/corner combinations.
An increasingly common technique to reduce dynamic power is the use of multiple voltage islands (domains), which allow some blocks to use lower supply voltages than others, or to be completely shut off for certain modes of operation. This flow gets even more complex when dynamic voltage scaling is used to change the supply voltage level during operation.
Multi-voltage flows present new challenges in physical design. Firstly, the tools need to correctly place and route across multiple domains and ensure that the timing and optimization engines honor the multi-voltage domain specifications. Secondly, they need to ensure that the multi-mode multi-corner requirements are also satisfied in the same run. Basically, each additional voltage island causes the number of timing analysis mode/corner scenarios to double when all the min/max voltage combinations are considered.