|Olympus-SoC Low-Power Platform||Datasheet||IC Design|
|Olympus-SoC Overview||Technology Overview||IC Design|
|Power Aware Verification||On-demand Web Seminar|
|Power Efficient Design Challenges and Trends||On-demand Web Seminar||ESL , Silicon Test and Yield Analysis , IC Design|
|Power-Aware Silicon Test: Understanding Testing and Power-Sensitive Designs||On-demand Web Seminar||Silicon Test and Yield Analysis|
|Questa Platform Datasheet||Datasheet||Functional Verification|
|Re-defining Verification Performance||Technology Overview||Functional Verification|
|Signal Integrity Optimization with Olympus-SoC||White Paper||IC Design|
|To Retain or Not to Retain: How Do I Verify the State Elements of My Low Power Design?||White Paper||Functional Verification|
|Understanding the Low Power Abstraction||White Paper||IC Design|
Low Power Solutions
A new generation of tools from Mentor has recently debuted that delivers modeling fidelity and simulation performance at the early design exploration stage.
Mentor’s power aware simulation gives designers the ability to functionally verify their power management techniques at the RTL, reducing costs significantly both in terms of effort and time.
Mentor’s place and route solution, Olympus-SoC is UPF-compliant and handles a variety of low power design styles during placement, routing, and optimization.
Low Power ResourcesView On-demand Web Seminar View On-demand Web Seminar
- Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
- Mentor Graphics Provides Comprehensive Low Power Solution in TSMC Reference Flow 10.0
- Mentor Graphics Launches Precise-IP Vendor-independent IP Platform for FPGA Design
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions Limited for Design and Consulting Services