|How Physical Implementation realizes Power Intent||On-demand Web Seminar||IC Design|
|How do we get 'Intelligence' into the Business of Electronics Manufacturing?||White Paper||Valor MSS PCB Manufacturing Systems Solutions|
|Improving Circuit Reliability with Calibre PERC||On-demand Web Seminar||IC Design|
|Low Power Design and Verification Techniques||White Paper||Functional Verification|
|Low-Power Physical Design with Olympus-SoC||White Paper||IC Design|
|Mentor Graphics Low Power Design Press Conference, DAC 2009||Technology Overview||ESL|
|ModelSim Simulation of Waveforms and Debug Demo for Beginners||Product Demo||Functional Verification|
|Multi-Corner-Multi-Mode P&R for Timing, Power, and SI Closure||On-demand Web Seminar||IC Design|
|Nucleus Power Management Demystified: Concepts||Technology Overview||Embedded Software|
Low Power Solutions
A new generation of tools from Mentor has recently debuted that delivers modeling fidelity and simulation performance at the early design exploration stage.
Mentor’s power aware simulation gives designers the ability to functionally verify their power management techniques at the RTL, reducing costs significantly both in terms of effort and time.
Mentor’s place and route solution, Olympus-SoC is UPF-compliant and handles a variety of low power design styles during placement, routing, and optimization.
Low Power ResourcesView On-demand Web Seminar View On-demand Web Seminar
- Mentor Graphics Announces the First IP to System, UPF-based Low-power Verification Solution
- Mentor Graphics Questa Functional Verification Platform Selected by Cypress Semiconductor
- Mentor Graphics Provides Comprehensive Low Power Solution in TSMC Reference Flow 10.0
- Mentor Graphics Launches Precise-IP Vendor-independent IP Platform for FPGA Design
- Mentor Graphics Catapult C Synthesis Selected by Fujitsu Microelectronics Solutions Limited for Design and Consulting Services