The semiconductor industry can (and does) argue about when extreme ultraviolet lithography will be ready for production. However, the actual dates are irrelevant to those engineers who must prepare OPC tools and processes for the EUV-specific effects that will have to be managed in manufacturing. They are busy now, evaluating the impact of such challenges as the distortion caused by EUV shadowing. In … Read More
Tools, resources and expertise to help fabless IC designers create successful IC products.
David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More
The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the … Read More
In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently … Read More
Are you a TSMC customer or partner? If so, you’ll want to take a look at our presentations from the 2013 TSMC Open Innovation Platform conference. Design Reliability with Calibre YieldEnhancer/SmartFill and Calibre PERC Broadcom & Mentor Graphics The complexity of advanced technologies drives new requirements for poly/OD and metal fill to solve critical manufacturing effects, and more importantly … Read More
At advanced nodes, variability issues lurk behind every design mode, power state, process condition, and manufacturing step. Yet designers must find a way to balance the optimization of multiple operational modes and design corners against the aggressive performance and power targets demanded by today’s fast-moving markets. Concurrent analysis and optimization during place and route operations can provide … Read More
The number of electronic devices used in vehicles is increasing exponentially, for everything from braking to engine control to navigation to collision avoidance. Devices used in safety-critical applications like these not only require very high quality testing at the time of manufacture, but also built-in self-test capability, so they can be tested within the safety-critical application. Advanced design-for-test … Read More
Are you attending the SPIE Advanced Lithography conference beginning Feb 23rd? If so, you’ll want to take note of the following Mentor presentations…there’s something for everyone. For detailed abstracts, go to the SPIE Technical Summaries document. Feb 25, 4:40pm: Feasibility of compensating for EUV field edge effects through OPC Feb 25, 5:20pm: Pattern fidelity verification for logic design in EUV … Read More
Download the latest version of our guide to multi-patterning design and debugging, containing links to all of David Abercrombie’s detailed educational articles on SemiEngineering.com, along with links for complementary reference and learning options. Whether you are already working on designs with multi-patterning requirements, or just beginning multi-patterning work, you will benefit from David’s … Read More
Diamonds may not be a designer’s best friend when debugging triple patterning errors. Triple patterning violations can be quite complex, and debugging can be tricky, but the challenges are manageable with software that helps the designer understand the design issues. Learn how to recognize and avoid triple patterning traps in part 2 of The Trouble with Triples on SemiEngineering by multi-patterning … Read More
Foundries, both pure-play and independent device manufacturers (IDM), rigorously compete for market share. One factor that helps them get and keep business is turnaround time (TAT). Until recently, companies could reduce TAT by adding computer hardware, fine-tuning OPC recipes, improving input hierarchical handling of designs, and upgrading to new software versions with new functionality and performance … Read More
Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference. Design Reliability with Calibre YE-SmartFill and Calibre PERC (Broadcom & Mentor Graphics) New methodologies were developed for 28nm designs using Calibre SmartFill and Calibre PERC. Calibre SmartFill was deployed to meet the new strict DFM requirements … Read More
With the move to small geometries, existing fault models such as stuck-at, transition, bridging, open, and small-delay are becoming less effective at ensuring desired quality levels. While these models only consider faults on cell inputs/outputs and interconnect lines between cells, more defects increasingly occur within the cell structures. A new cell-aware test that directly targets specific shorts, … Read More
All the major foundries have announced FinFET technologies. FinFETs hold the promise of lower power usage and better area utilization, as well as traditional scaling improvements. Aaaaand…the thought of implementing them may be scaring the willies out of a lot of designers. How do I design these things? How do I know what the design needs? How do I verify them? Well, first, take a deep breath. … Read More
What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More
- EUV...Ready or Not?
- Lights! Camera! Multi-Patterning!
- Vector? Vectorless? What’s a power grid to do?
- Esperanto for ICs
- Mentor's TSMC OIP Presentations Now Available!
- Variability is EVERYWHERE!
- Is your car safe to drive? Are you sure?
- I SPIE, with my little eye...
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- March, 2014
- February, 2014
- January, 2014
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- A Little Bit Here, A Little Bit There...Calibre Cluster Manager Reduces Turnaround Time
- TSMC OIP presentations now available!
- Can You Benefit from Cell-Aware Test?
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- How Do I?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- May, 2013
- April, 2013
- March, 2013
- May, 2009