Tools, resources and expertise to help fabless IC designers create successful IC products.
3D-stacked designs containing a mix of separate logic and memory die represent a somewhat new application for memory BIST (built-in self-test), compared to the more conventional single-die embedded SRAM implementations. Gaining access to a DRAM requires predefined customized memory operations that provide a cost-effective solution for testing 3D ICs. EDA tools must make this definition step as simple as possible, while ensuring it can be reused across designs and over time. Read more
2.5D/3D power grid analysis requirements are well beyond the simple power model-based analysis tools currently available, especially when considering that power is one of the biggest challenges in 2.5D/3D IC implementations. Vertical IC integration is already enabling specific applications, such as sensor-on-chip, stacked memories, and wide IO. PGA software must be extended and enhanced to fulfill the new requirements and use models related to 2.5D/3D IC systems, especially if the goal is to have a true homogeneous 3D IC integration flow with multi-die, robust power grid floorplanning capability. Read more
A number of techniques have been developed by electronic design automation (EDA) software suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing. The goal is to get maximum write time reduction at the lowest cost and with smallest impact to the running operation. This article describes and compares several techniques, and emerges with a clear recommendation. Read more
Automated pattern recognition capability can enable designers to find and analyze specific design patterns of interest (for instance, ESD protection schemes, or level shifters) quickly and efficiently. For ease of use, as well as broad applicability, designers need both the flexibility to define these patterns in a simple way (e.g., SPICE) that is independent of the design cell names, and the ability to define some margin around a design pattern, so that similar, but not exact, matches can be identified for analysis when appropriate. Read more
FinFETs, or so-called 3D transistors, are a key competitive element in all the leading-edge IC foundry offerings, because FinFETs can achieve much lower power operation than planar transistors. This panel discusses how FinFETs will change the design, verification, and test flow.
- Joe Sawicki, VP and General Manager of the Design to Silicon Division, Mentor Graphics
- KK Lin, Director of Design Enablement, Samsung
- Richard Trihy, Director of Design, GLOBALFOUNDRIES
- Indavong Vongsavady, Director at ST Central CAD and Design Solutions, STMicroelectronics
The IC industry will undergo significant changes as future growth is driven not just by traditional Moore’s Law scaling, but also by “More Than Moore” technologies, including 3D-IC, MEMS, and silicon photonics. This panel discusses the exciting opportunities and challenges ahead.
- John Ferguson, Director of Marketing, Calibre DRC Applications, Mentor Graphics
- Michael Hochberg, Director, OpSIS, University of Delaware
- Robert Patti, CTO and VP of Design Engineering, Tezzaron
- Suk Lee, Senior Director, Design Infrastructure Marketing Division, TSMC
Several high-growth IC markets are experiencing demand for higher reliability, including mobile/wireless, automotive, industrial control, and medical. At the same time, factors such as thinner gate oxide and multiple power rails have the potential to introduce new failure mechanisms. This panel discusses the demand for IC reliability, what design methodologies can reduce the occurrence of delayed failure mechanisms, and how design for reliability checks can be automated to help remove the burden from designers.
- Matt Hogan, Product Marketing Manager, Calibre Design Solutions, Mentor Graphics
- Ofer Tamir, Director of Design Enablement and Design Support, TowerJazz
- Ertugrul Demircan, PVG Manager, Freescale
- Tim Turner, Reliability Center Business Development Manager, College of Nanoscale Science and Engineering
Just when you thought you were getting used to double patterning requirements and processes, multi-patterning is now a reality. While the additional MP requirements at 16/14 nm weren't readily visible to the designer, anyone moving to the 10 nm process node will probably need some additional multi-patterning education. The 10 nm node introduces at least two new multi-patterning techniques you need to understand. Read more
David Abercrombie, DFM Program Manager for Calibre, is an expert at detailing the multifaceted impacts of multi-patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of multi-patterning, his articles provide a well-lit roadmap that enables them to not only comprehend how multi-patterning will change the design process, but also how they can anticipate and mitigate the potentially unwelcome effects, such as lengthy debugging of multi-patterning errors, or unforeseen influences on timing and performance. Additional resource links provide complementary learning options. Read more
The Calibre sign-off verification platform is integrated with a broad range of design tools used throughout the design flow. Extensible interfaces are available for custom design, place and route, and a wide range of specialty design tools. These interfaces let designers use Calibre’s sign-off engine flows from their favorite design cockpits, enabling early detection and correction of manufacturing issues. Read More