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Foundry Solutions

Tools, resources and expertise to help fabless IC designers create successful IC products.

21 Mar, 2014
Foundry Solutions

I See the Light!

Posted by Shelly Stalnaker

Shelly Stalnaker Photonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design. The biggest challenge in applying CMOS foundry processes to silicon photonics is creating … Read More

Foundry, IC Design, silicon photonics, waveguides, ic manufacturing, Michael White

20 Mar, 2014
Foundry Solutions

3D Yoga

Posted by Shelly Stalnaker

Shelly Stalnaker

I practice yoga because it helps with my flexibility. Of course, that’s a little like saying that lighting a candle helps with heating your house, but I digress. The point is, flexibility is generally a good thing, and that holds true for 3D ICs and their test strategies. As discussed in the Electrical Engineering Journal, a flexible 3D test strategy that uses a “plug-and-play” architecture

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Silicon Test, Etienne Racine, IC test, 3DIC, Martin Keim, Ron Press, IEEE P1687, IJTAG

19 Mar, 2014
Foundry Solutions

Déjà Vu All Over Again

Posted by Shelly Stalnaker

Shelly Stalnaker Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm … Read More

Foundry, IC Design, 14nm, 16nm, 10nm, advanced node, leading-edge, Semiconductor, Christen Decoin, 20nm, technology node, 28nm

18 Mar, 2014
Foundry Solutions

Old Faithful

Posted by Shelly Stalnaker

Shelly Stalnaker While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More

IC Design, Foundry Solutions, IC Verification, 16nm, 20nm, 10nm, circuit, PERC, Reliability, electrical, 45nm, Verification, Calibre

17 Mar, 2014
Foundry Solutions

Little Orphan Annie

Posted by Shelly Stalnaker

Shelly Stalnaker

Is design-for-test the forgotten stepchild of IC design? Not any more, and DFT engineers can, in large part, thank the automotive industry. The number of processors built into a vehicle is steadily increasing, as we all know (okay, maybe not that guy driving the 1969 Chevy Camaro). These chips have to meet very high standards for quality and reliability, which means the companies who make them need

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automotive test, Silicon Test, Cell-Aware ATPG, cell-aware, ATPG, logic BIST, Cell Aware Test, Ron Press, embedded compression, semiconductor test, iso26262

14 Mar, 2014
Foundry Solutions

Are You ECO-Friendly?

Posted by Shelly Stalnaker

Shelly Stalnaker Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More

P&R, Jeff Wilson, place and route, 45nm, 20nm, IC Design, smart fill, ic manufacturing, DRC, ECO fill

3 Mar, 2014
Foundry Solutions

EUV...Ready or Not?

Posted by Shelly Stalnaker

Shelly Stalnaker The semiconductor industry can (and does) argue about when extreme ultraviolet lithography will be ready for production. However, the actual dates are irrelevant to those engineers who must prepare OPC tools and processes for the EUV-specific effects that will have to be managed in manufacturing. They are busy now, evaluating the impact of such challenges as the distortion caused by EUV shadowing. In … Read More

SRAF, scanner, EUV shadowing, extreme ultraviolet, EUV, mask, OPC, ic manufacturing, Lithography

3 Mar, 2014

Shelly Stalnaker David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More

double patterning, EUV, 20nm, Multi-Patterning, triple patterning, IC Design, ic manufacturing

19 Feb, 2014

Shelly Stalnaker The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the … Read More

IC Design, IC Verification, dynamic power grid analysis, vcd, vectorless verification, power grid analysis, value change dump

18 Feb, 2014
Foundry Solutions

Esperanto for ICs

Posted by Shelly Stalnaker

Shelly Stalnaker In Standards & Travels on EE Times, Bruce Swanson reminisces about a trip he took to Europe, long before there were cell phones, a common currency, or even the Internet. Dealing with different languages, different currencies, and different local customs took time, was a bit frustrating, and sometimes led to mistakes (WHERE is this train going?!). His experiences on that trip came to mind recently … Read More

IEEE standard, IJTAG, desgin for test, yield analysis, P1687, Silicon Test

14 Feb, 2014
Foundry Solutions

Variability is EVERYWHERE!

Posted by Shelly Stalnaker

Shelly Stalnaker At advanced nodes, variability issues lurk behind every design mode, power state, process condition, and manufacturing step. Yet designers must find a way to balance the optimization of multiple operational modes and design corners against the aggressive performance and power targets demanded by today’s fast-moving markets. Concurrent analysis and optimization during place and route operations can provide … Read More

place and route, design corners, IC Design, concurrent analysis, Olympus-SoC, P&R, IC Verification, mcmm

13 Feb, 2014

Shelly Stalnaker The number of electronic devices used in vehicles is increasing exponentially, for everything from braking to engine control to navigation to collision avoidance. Devices used in safety-critical applications like these not only require very high quality testing at the time of manufacture, but also built-in self-test capability, so they can be tested within the safety-critical application. Advanced design-for-test … Read More

13 Feb, 2014

Shelly Stalnaker Are you attending the SPIE Advanced Lithography conference beginning Feb 23rd? If so, you’ll want to take note of the following Mentor presentations…there’s something for everyone. For detailed abstracts, go to the SPIE Technical Summaries document. Feb 25, 4:40pm: Feasibility of compensating for EUV field edge effects through OPC Feb 25, 5:20pm: Pattern fidelity verification for logic design in EUV … Read More

29 Jan, 2014

Shelly Stalnaker Download the latest version of our guide to multi-patterning design and debugging, containing links to all of David Abercrombie’s detailed educational articles on SemiEngineering.com, along with links for complementary reference and learning options. Whether you are already working on designs with multi-patterning requirements, or just beginning multi-patterning work, you will benefit from David’s … Read More

triple patterning, double patterning, IC Design, Debugging, Physical Verification, SADP, ic manufacturing, Multi-Patterning

27 Jan, 2014

Shelly Stalnaker Diamonds may not be a designer’s best friend when debugging triple patterning errors. Triple patterning violations can be quite complex, and debugging can be tricky, but the challenges are manageable with software that helps the designer understand the design issues. Learn how to recognize and avoid triple patterning traps in part 2 of The Trouble with Triples on SemiEngineering by multi-patterning … Read More

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