You’re creating chips with high functionality, multiple operating modes, low power consumption and extreme reliability—pushing the manufacturing process to the limit.
But your advanced ICs are increasingly sensitive to the smallest manufacturing variations, and that affects both performance and yield. Simply increasing guard bands does not effectively deal with variability…and it diminishes your competitive advantage. How do you deal effectively with variability and maintain your competitive edge in a nanometer world?
Manufacturing Variability Challenges
Mentor Graphics has answers to your most challenging questions:
Initial Design
- How can I create a high-yield design without sacrificing performance?
- How can I avoid manufacturing variability problems from the start?
- How can I reach design closure faster, and with higher confidence?
Design Fabrication
- How can I get my mask flow ready for the next node?
- How can I speed up my mask flow?
- How can I manage the cost of computing associated with mask prep?
Design Enhancement
- How can I avoid manufacturing surprises that delay my volume ramp?
- How can I incorporate specific foundry information into my design?
- How can I quickly find and fix the most sensitive design features?
- How can I get the best possible performance from my design?
Yield Ramp
- How can I accelerate my yield learning curve?
- How can I pinpoint the root cause of yield problems?
- How can I lower my defect escape rate and still keep test costs down?
Understanding how manufacturing variability affects both functional and parametric yield will help ensure your success. To get you there, we provide:
Compatible, Complementary Tool Suites
- Our tools extend across the entire physical implementation lifecycle, starting with cell library development, and continuing through place and route, physical verification, layout optimization, mask preparation, testing and failure analysis.
Solutions that Address the Full Range of Manufacturing Variability Issues
- Random particle defects
- Small-scale device and interconnect interactions
- Lithographic distortions
- Thickness variations due to chemical/mechanical polishing and unevenness in film deposition and etch rates
Accurate Models and Algorithms
- Our solutions are calibrated to real production data to accurately predict process variability and identify problematic design features.
- Incorporating accurate Mentor models into your design flow allows you to prioritize your design activities and decisions for maximum business advantage.
Mentor Graphics solutions can help you get the answers you need to make informed choices throughout your design process.
Mentor Graphic Design-to-Silicon Solution Flow (Click to View Larger)
Meeting the Critical Challenges of IC Implementation
Video: Joe Sawicki, V.P. and General Manager of Mentor’s Design-to-Silicon Division, describes how Mentor is driving toward the integration of its IC implementation platforms. View Video
News and Press
- SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs (May 22, 2012)
- GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC (May 22, 2012)
- TowerJazz Finds a Unique Solution for Advanced ESD and Power Domain Checking in Calibre PERC (May 22, 2012)
Manufacturing Variability Challenges
Design
Mentor’s variability-aware/timing-aware place and route system delivers “correct-by-construction” layouts concurrently optimized for both performance and yield across any number of modes and corners.
Enhance
Mentor’s Calibre® platform provides the fastest, most accurate, and most reliable integrated verification, extraction and design-for-manufacturing (DFM) platform for both library cells and full chips.
Fabricate
Mentor’s fast, accurate, and cost-effective mask resolution enhancement and data prep flows ensure quick mask turnaround and high manufacturability at 65 nm, 45 nm, 32 nm and beyond.
Ramp
Mentor’s production yield solution combines the power of diagnosis-driven yield analysis and high-quality manufacturing test to accelerate yield ramp.
Manufacturing Variability Resources
Assessment and comparison of different approaches for mask write time reduction
White Paper: The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout,... View White Paper
Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?
White Paper: Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper
News
- TowerJazz Finds a Unique Solution for Advanced ESD and Power Domain Checking in Calibre PERC
- SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs
- GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC
- Mentor Embedded Continues to Simplify Linux and Open Source Development with Support of the Yocto Project
View all Manufacturing Variability Resources: White Papers, Datasheets, Web Seminars, and more