If you’re designing large die such as a system-on-chip (SoC) with high power demands, you’d better be thinking about how to get the heat out. Poor heat dissipation can lead to a sub-optimal packaging solution from cost, size, weight and performance perspectives. Historically, designers assumed the die temperature was uniform. Not any more. Heating due to current leakage makes power dissipation … Read More
Fabless/Foundry Ecosystem Solutions
IC design, verification, and test tools, resources, and expertise to help fabless designers create successful IC, IP, and SoC products manufactured at the world’s leading foundries.
No, that’s not really a cry for help, at least not from me. But I can imagine a lot of designers saying just that as they try to understand and implement multi-patterning requirements. LELE? LELELE? LELELELE? SADP? SADP SIT? Whhaaaatttt???!!! And help we have. In spades. Our resident multi-patterning expert, David Abercrombie, not only writes extensively about multi-patterning issues, but he is … Read More
The World Cup is here! Every four years, the culmination of hundreds of qualifying matches around the world brings the best national teams together for nearly a month of intense competition to determine the world champion football team (Sorry, USA, but it’s football everywhere else). New national uniforms are unveiled, shoe companies vie to sponsor the best players and teams with their most advanced … Read More
With the advent of advanced process nodes, IC design teams have an increasing ability to pack more functionality and performance into state-of-the art SoCs. At the same time, every new node transition brings a flood of new design challenges that can severely impact design performance, power, and time-to-market. The introduction of multi-patterning, FinFET devices, complex DRC/DFM requirements, increased … Read More
Remember learning your colors in kindergarten? Learning how to debug color assignment errors in multi-patterning can sometimes seem just as confusing. In Take Two of the Tech Talk videos on multi-patterning, David Abercrombie continues his discussion with Brian Bailey of Semiconductor Engineering about color assignment issues, and possible corrective actions. More often than not, a color assignment … Read More
Depending on how well your company implements it, verification can be a quagmire that slows down your design delivery and creates frustration and conflict between teams, or a springboard that lets you deliver high-quality designs ahead of your competition. In a recent interview with Pradeep Chakraborty, our CEO, Wally Rhines, discusses the intricacies of design verification today, the biggest verification … Read More
Photonics technology isn’t new, by any means, but what is new is the drive to leverage high-volume silicon-based semiconductor manufacturing foundries and processes to build chips that can create, sense, modulate, and transmit light. So says Michael White in his latest SiliconEdge column on Electronic Design. The biggest challenge in applying CMOS foundry processes to silicon photonics is creating … Read More
I practice yoga because it helps with my flexibility. Of course, that’s a little like saying that lighting a candle helps with heating your house, but I digress. The point is, flexibility is generally a good thing, and that holds true for 3D ICs and their test strategies. As discussed in the Electrical Engineering Journal, a flexible 3D test strategy that uses a “plug-and-play” architecture… Read More
Trailblazers, followers, and stragglers…semiconductor companies have usually always sorted themselves out along these lines. At 20nm, though ,we’re beginning to see a shift in these classifications that is affecting both technology node adoption and market strategy. Only a few companies are moving to nodes at 20nm and below, while many of the typical followers have decided to stay at 28nm … Read More
While unpredictability may account for the lure of gambling, reliability is an essential part of our everyday lives. Yellowstone National Park, which sits above the Yellowstone Caldera, contains half of the world’s geothermal features. Among the most famous is Old Faithful, a huge geyser that erupts at regular intervals. One reason tourists flock from all over the world to this park is that they know … Read More
Is design-for-test the forgotten stepchild of IC design? Not any more, and DFT engineers can, in large part, thank the automotive industry. The number of processors built into a vehicle is steadily increasing, as we all know (okay, maybe not that guy driving the 1969 Chevy Camaro). These chips have to meet very high standards for quality and reliability, which means the companies who make them need… Read More
Every designer dreads the last-minute engineering change order, or ECO. Just when you think you’re done…you’re not. At 45nm and below, ECOs get even more difficult to implement, because fill now has a direct impact on design performance. A small re-routing can get complicated very quickly with the complex fill requirements of advanced nodes. Fortunately, help is available! On Semiconductor … Read More
The semiconductor industry can (and does) argue about when extreme ultraviolet lithography will be ready for production. However, the actual dates are irrelevant to those engineers who must prepare OPC tools and processes for the EUV-specific effects that will have to be managed in manufacturing. They are busy now, evaluating the impact of such challenges as the distortion caused by EUV shadowing. In … Read More
David Abercrombie recently met with Brian Bailey of Semiconductor Engineering to explain many of the concepts and issues of multi-patterning that he has been writing about for the last couple of years. If you want to understand the basics of multi-patterning requirements, 12 minutes is all you need to check out their first video: Tech Talk: Multipatterning on semiengineering.com. If the video piques … Read More
The terms vector and vectorless modes are commonly used in the context of dynamic power grid (PG) analysis, but what do these terms mean? The PG dynamic simulator uses a design’s activity suite to compute the voltages and currents in the PG network. In vector mode, typically referred as a value change dump (VCD), logic simulation is used to generate the complete activity suite. In vectorless mode, the … Read More
- July, 2014
- June, 2014
- May, 2014
- March, 2014
- February, 2014
- January, 2014
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- A Little Bit Here, A Little Bit There...Calibre Cluster Manager Reduces Turnaround Time
- TSMC OIP presentations now available!
- Can You Benefit from Cell-Aware Test?
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- How Do I?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- May, 2013
- April, 2013
- March, 2013
- May, 2009