Foundry Solutions
Foundry Solutions
Tools, resources and expertise to help fabless IC designers create successful IC products.
Event
Mentor Partner Activities at DAC
Mentor will be describing recently collaborations with strategic partners including ARM, TSMC, GLOBALFOUNDRIES, and TowerJazz at this year's Design Automation Conference in Austin (June 3-5). Details
Expert panel discusses the new physical challenges of IC design at 14nm
IC designs at 14nm will have new structures and new techniques that impact routing, design for manufacturing, extraction and verification. This expert panel discusses the intricacies of IC design at 14nm and how the design enabling and manufacturing flow will change to meet the new physical challenges. Panelists:
- Paul Dempsey, Editor-In-Chief, Tech Design Forum (moderator)
- Jean-Pierre Geronimi, Special Project Director in Central CAD and Design Solutions, STMicroelectronics
- Dipesh Patel, Deputy General Manager, Physical IP Division, ARM
- Joseph Sawicki, VP and GM Design to Silicon Division, Mentor Graphics
- Lars Liebmann, Distinguished Engineer, IBM
Technical Article
Diagnosing Complex Hold Time Faults in ICs
If a signal on clock tree is slower than expected due to either a design error or a manufacturing defect, it may cause complicated fault behaviors during scan-based testing. This paper illustrates the failure behaviors of such clock defects and propose an algorithm to diagnose it. Read more
Foundry Solutions Video Blog: TSMC OIP Conference
Technology Overview: At TSMC's Open Innovation Platform (OIP) Ecosystem Forum, Mentor made technical presentations on four different topics, two of them co-presented with TSMC and LSI Corporation. Those presentations are described... View Technology Overview
Technical Article
Creating Plug-and-Play IP Networks in Large SoCs with IEEE P1687 (IJTAG)
Integration and testing of IP blocks in large SOCs has been a manual, time consuming design effort. A new standard called IEEE P1687 (or "IJTAG") for IP plug-and-play integration was created to simplify these tasks and EDA tools are emerging to support the standard. IJTAG simplifies connecting any number of IJTAG-compliant IP blocks into an integrated, hierarchical network, allowing access to them from a single point. IJTAG saves engineering time and potentially can reduce test time and tester memory requirements. Read more
Technical Article
Improving Device Selection for IC Failure Analysis
Production test data can only be used to reduce the time spend in failure analysis and more quickly identify the root cause of IC manufacturing problems. This paper describes the use of diagnosis driven yield analysis to separate failed devices into systematic and random populations, so only systematic defects are submitted for failure analysis. The approach is demonstrated with two silicon case studies in which very subtle defects that would be difficult to identify with any other methodology are identified. Read more
Technical Article
Chasing DP Rabbits Without Falling Down a Rabbit Hole
The use of stitching can greatly reduce the number of double patterning (DP) decomposition violations that a designer has complexity-the decomposition tool must process many additional design rules to generate legal stitches, and know how to use them properly during coloring. Despite these immense complexities, it has been possible so far to produce automated tool functionality that captures and applies all of these rules to produce successful layer decompositions.
Double Patterning Exposed!!
Chasing Rabbits(SemiMD, March 21, 2013)
News of Interest
2013 Kaufman Award Winner to Speak at User2User
Come hear Mentor Graphics CEO, Wally Rhines, 2013 Kaufman Award Winner, Chenming Hu, and Xilinx Senior VP, Victor Peng, at the User2User Conference in San Jose. Read More
Technical Article
The Secrets of 14nm Lithography
Optical lithography is not dead yet! 193nm immersion lithography will be used for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm. Gandharv Bhatara explains how new OPC technology solves both the CD and turn-around time at very the edges of advanced node manufacturability. Read More
News of Interest
TSMC Technology Symposium
TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, power ICs, and MEMS.
Mentor Graphics will host a booth at the conference where you can learn more about Mentor's reference flows, and tools for Custom IC Design and simulation, IC verification, DFM, silicon testing and yield improvement. Experts will be available to discuss special topics such as advanced fill requirements, double patterning, design for reliability, cell-aware testing and IJTAG. Learn more and register
Technical Article
A New World for Fill at N20
There are many major changes required to design, verify, and manufacture semiconductors at the 20nm process node (N20). One of these is fill. At previous design nodes, fill was used just to ensure manufacturability by giving each layer (metal, poly, diffusion) an accepted density. At N20, fill is used to address many more manufacturing issues, and has become highly complex. Read More
Technical Paper
Mentor and GLOBALFOUNDRIES Use Layout-Aware Scan Diagnosis to Find Yield Issues in Designs
Mentor and GLOBALFOUNDRIES have worked together to validate some new tools for learning the root cause of failing devices that may be a result of critical design features. The method is based on the use of layout design data and diagnosis of scan tests on actual product parts that have failed. Experimental data from simulations as well as a silicon case study on a 28nm product qualification vehicle demonstrate the effectiveness of the method. Read More
On-Demand Web Seminar
Finding and Fixing Double Patterning Errors in 20nm Design
New to Double Patterning? Start HERE!
Selected by attendees as the "Customers' Choice" presentation at TSMC's Open Innovation Platform Forum, David Abercrombie's introduction to double patterning debugging explains why and how double patterning errors are created, and what you can do to correct them. Because double patterning errors often have multiple causes AND solutions, debugging can be tricky. David's step-by-step explanations will help you acquire and apply new DP expertise right away. View this on-demand webinar at your convenience! View On-demand Web Seminar
Technical Paper
Mentor, TSMC and AMD Collaborate on Rapid Physical Failure Analysis
TSMC, AMD and Mentor Graphics use layout-aware diagnosis to increase the efficiency of their Physical Failure Analysis efforts. Information from the physical design combined with production test failure diagnosis can be fed into sophisticated statistical software that determines the types and location of defects, and identifies which failed die should be selected for PFA.
Expert’s Corner
Double Patterning Exposed!!
David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning, these articles provide a well-lit roadmap that enables them to not only comprehend how double patterning will change the design process, but also how they can anticipate and mitigate the potentially unwelcome effects, such as lengthy debugging of double patterning errors, or unforeseen influences on timing and performance. Read more
Technical Paper
GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs
At 28/20nm, manufacturing becomes much more sensitive to specific yield limiting features. GLOBALFOUNDRIES and Mentor Graphics are using layout-aware scan diagnosis to identify critical features and accelerate yield ramps.
Mentor @ the TSMC Open Innovation Platform Forum
A Platform for TSMC’s CoWoS 3DIC Reference Flow
The first phase of 3DIC adoption will be based on silicon interposers. Designing multi-die systems using this technology introduces new challenges for the EDA design flow. At the TSMC OIP event, Mentor described solutions for 3DIC design specifically tailored to TSMC manufacturing processes. View Presentation
Mentor @ the TSMC Open Innovation Platform Forum
Automated Approach for Waiving Physical Verification Errors in IP
Redundantly reviewing recurring errors during custom and third-party IP integration can slow down SoC verification. An automated waiver management methodology enables design and verification teams to specify and process a variety of design rule waivers, reducing debugging time and improving SoC results. Mentor and LSI recently described the use of this technology at the TSMC OIP event. View Presentation
Mentor @ the TSMC Open Innovation Platform Forum
Improving IC Design for Reliability
Verification of 20nm designs is expected to bring significant challenges. A robust verification methodology that addresses circuit reliability is increasingly difficult. At 20nm, new devices that incorporate thin oxides are less robust and more subject to electrical overstress (EOS) failures. The increased use of mixed-signal and multi-voltage design techniques also increases the likelihood that transistors could be implemented in an incorrect voltage domain. At TSMC's recent OIP event, Mentor showed techniques to prevent long term electrical failure using new tools to validate ESD structures, protect against EOS, manage multiple power domains, and carefully balance sensitive analog circuits. View Presentation