Foundry Solution Archive
|1/31/2013||Mentor's Tessent Racks Up Two More Awards|| |
At the annual DesignVision and Best in Test awards reception, Mentor Graphics' test products scored two wins: a DesignVision award for their new Tessent IJTAG product, and a Best in Test award for cell-aware (aka cell-internal) testing.
|Tessent, IC test, IJTAG, IP, IP integration, cell-aware, UDFM|
|1/29/2013||SPIE Papers Show High Interest in DFM|| |
While the SPIE Advanced Lithography conference best known for IC manufacturing, computational lithography, mask preparation and other back-end topics, there is also a significant amount of interest in Design for Manufacturing (DFM) at the conference. Some litho issues are best (or only) addressed by modifying the physical design or layout. At the upcoming SPIE Conference (Feb 24-28, San Jose Convention Center), Mentor will be presenting three papers on DFM:
|lithography, SPIE, DFM, layout dependemt effects, LDE, arrays, layout, litho hotspot, 20nm, 14nm|
|1/15/2013||Need a Faster Way to Perform High Frequency Analysis on AMS ICs?|| |
IC designers often use empirical approaches to perform High Frequency Analysis (HFA) on passive devices, which can be slow and inaccurate. Mentor is exploring a new approach that provides a scalable tool flow with 10X capacity and performance improvement over TCAD tools and the accuracy needed for rapid device exploration. The flow includes 1) device detection and extraction with Calibre LVS and Calibre PERC, 2) interconnect RLC extraction with Calibre xRC, Calibre xACT-3D and Calibre xL, 3) 3D-IC design rule checking with Calibre 3DSTACK, and 4) design environment integration with Calibre Interactive.
|high frequency analysis, HFA, passive device, TCAD, rapid exploration|
|1/7/2013||Mentor, TSMC and AMD Collaborate on Rapid Physical Failure Analysis||TSMC, AMD and Mentor Graphics use layout-aware diagnosis to increase the efficiency of their Physical Failure Analysis efforts. Information from the physical design combined with production test failure diagnosis can be fed into sophisticated statistical software that determines the types and location of defects, and identifies which failed die should be selected for PFA.||foundry, layout-aware diagnosis, failure analysis, PFA, TSMC, AMD|
|12/3/2012||Double Patterning Exposed!!||David Abercrombie, DFM Program Manager for Calibre, has written a series of articles detailing the multifaceted impacts of double patterning on advanced node design and verification. For designers struggling to understand the complexity and nuances of double patterning, these articles provide a well-lit roadmap that enables them to not only comprehend how double patterning will change the design process, but also how they can anticipate and mitigate the potentially unwelcome effects, such as lengthy debugging of double patterning errors, or unforeseen influences on timing and performance.||double patterning, lele, multi-patterning, multipatterning, DP, DPT, 20nm|
|11/20/2012||GLOBALFOUNDRIES and Mentor Develop Methods to Identify Critical Features in IC Designs||At 28/20nm, manufacturing becomes much more sensitive to specific yield limiting features. GLOBALFOUNDRIES and Mentor Graphics are using layout-aware scan diagnosis to identify critical features and accelerate yield ramps.||foundry, yield, scan diagnosis, globalfoundries|
|10/29/2012||A Platform for TSMC’s CoWoS 3DIC Reference Flow||The first phase of 3DIC adoption will be based on silicon interposers. Designing multi-die systems using this technology introduces new challenges for the EDA design flow. At the TSMC OIP event, Mentor described solutions for 3DIC design specifically tailored to TSMC manufacturing processes.||3D-IC, 3DIC, CoWoS, TSMC, die stacking, silicon interposer, foundry|
|10/19/2012||Automated Approach for Waiving Physical Verification Errors in IP||Redundantly reviewing recurring errors during custom and third-party IP integration can slow down SoC verification. An automated waiver management methodology enables design and verification teams to specify and process a variety of design rule waivers, reducing debugging time and improving SoC results. Mentor and LSI recently described the use of this technology at the TSMC OIP event.||waiver, IP, intellectual property, DRC, design rule check, Calibre, foundry|
|10/19/2012||Improving IC Design for Reliability||Verification of 20nm designs is expected to bring significant challenges. A robust verification methodology that addresses circuit reliability is increasingly difficult. At 20nm, new devices that incorporate thin oxides are less robust and more subject to electrical overstress (EOS) failures. The increased use of mixed-signal and multi-voltage design techniques also increases the likelihood that transistors could be implemented in an incorrect voltage domain. At TSMC's recent OIP event, Mentor showed techniques to prevent long term electrical failure using new tools to validate ESD structures, protect against EOS, manage multiple power domains, and carefully balance sensitive analog circuits.||reliability, circuit checking, PERC|