What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More
Foundry Solution Blog
Posts tagged with 'Design Rule Checking'
DRC- and DFM-clean designs can still have hundreds to thousands of violations that must be debugged and corrected. How? Why? Mismatches between a router’s simplified tech file and the complete (and complex) signoff design rule decks at advanced nodes are generating significant numbers of DRC/DFM errors that can wreak havoc on your tapeout schedules. In particular, we’re seeing greater visibility … Read More
Just like blueprints give an architect a visual representation of a building, design patterns provide engineers with a visual depiction of complex layout geometries. Design patterns have become a useful tool throughout design, verification, and test processes. This Design-to-Silicon white paper explains how Calibre Pattern Matching software can help you implement automated pattern capture and pattern … Read More
Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More
It is no mystery that the number of design rules has exploded over the past few technology nodes. It’s impossible for any human designer to “remember” them all, much less follow them all. It’s also a problem for the CAD engineer. We extracted some data from a spectrum of DRC decks that our customers have in production and the graph below shows the results. DRC Rule Count and Complexity by Technology… Read More
- Friendly but Shy Bears, and other EOS/ESD Issues
- It's Electrifying!
- Manage Your Stress...Advice from the Experts
- Testing the Boundaries of Good Design
- Making the Impossible -- Dealing with Patterns Throughout the Design and Manufacturing Flow
- Failing to Succeed
- Global Warming
- Won't You Please, Please Help Me?
- A Raft for a Flood - FinFET and Multi-Patterning Aware Place & Route
- September, 2014
- August, 2014
- July, 2014
- June, 2014
- May, 2014
- March, 2014
- February, 2014
- January, 2014
- UPDATE: Multi-Patterning Unmasked!!
- The Trouble with Triples—Part 2
- A Little Bit Here, A Little Bit There...Calibre Cluster Manager Reduces Turnaround Time
- TSMC OIP presentations now available!
- Can You Benefit from Cell-Aware Test?
- FinFET Fever...or FinFET Fear?
- 2014 is Underway! What's on Your Calendar?
- Routing Closure Challenges at 28nm and Below
- How Do I?
- Are you the 1%?
- Low Power, High Performance Design, Verification, and Test
- December, 2013
- Qualification Is Just the Beginning
- Pattern Matching: Blueprints for Further Success
- Mastering the Magic of Multi-Patterning
- The Trouble With Triples—Part 1
- Reducing the Tapeout Crunch with Signoff Confidence
- Foundry Solutions Video Blog: Calibre PERC
- Customizing Calibre Jobs without Editing Rule Decks
- Model-Based Hints: GPS for LFD Success
- October, 2013
- September, 2013
- May, 2013
- April, 2013
- March, 2013
- May, 2009