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Foundry Solution Blog

Posts tagged with 'Design Rule Checking'

15 Jan, 2014

Shelly Stalnaker What’s coming in 2014? What new challenges await? Are you ready? Get a heads-up on some of the trends and events of the next 12 months with two articles. First, if you’re contemplating, or already working on, 2.5D and 3D ICs, you should take a look at 3D IC Design: Outlook for 2014 on 3D InCites. Written by Joseph Sawicki, this article can help you prepare for your 3D IC implementations. … Read More

Design for Manufacturing, Calibre, Design Rule Checking, 14nm, IC Design, 16nm, IC Verification, MEMs, 10nm, Physical Verification, 3D-IC, DRC, 3DIC, FinFET, 2.5D, Foundry, 20nm

15 Jan, 2014

Shelly Stalnaker DRC- and DFM-clean designs can still have hundreds to thousands of violations that must be debugged and corrected. How? Why? Mismatches between a router’s simplified tech file and the complete (and complex) signoff design rule decks at advanced nodes are generating significant numbers of DRC/DFM errors that can wreak havoc on your tapeout schedules. In particular, we’re seeing greater visibility … Read More

tech file, tapeout, DRC, Design Rule Checking, P&R, signoff, IC Design, IC Verification

13 Dec, 2013

Shelly Stalnaker Just like blueprints give an architect a visual representation of a building, design patterns provide engineers with a visual depiction of complex layout geometries. Design patterns have become a useful tool throughout design, verification, and test processes. This Design-to-Silicon white paper explains how Calibre Pattern Matching software can help you implement automated pattern capture and pattern … Read More

pattern capture, Mentor Graphics, Pattern Matching, D2S, Design Rule Checking, Calibre Pattern Matching, SVRF, Foundry, hotspot detection, yield detractors, design waivers, DRC

13 Dec, 2013

Shelly Stalnaker Jean-Marie Brunet examines the reasons why the “tapeout crunch” is getting worse and worse at advanced nodes, and suggests some possible solutions, in this forward-looking article written for SemiconductorEngineering.com. … Read More

DRC, digital IC, Foundry, tech files, tapeout, 14nm, rule decks, signoff, 16nm, SoC, 10nm, SVRF, IP, Design Rule Checking, P&R, router, 20nm, Routing, Debugging

15 May, 2009

David Abercrombie

It is no mystery that the number of design rules has exploded over the past few technology nodes. It’s impossible for any human designer to “remember” them all, much less follow them all. It’s also a problem for the CAD engineer. We extracted some data from a spectrum of DRC decks that our customers have in production and the graph below shows the results. DRC Rule Count and Complexity by Technology

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Physical Verification, Design Rules, DRC, Design Rule Checking

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