Improve Your Competitiveness with Faster Time-to-Mask

Every new technology node brings a growing set of challenges to overcome. Yet technology ramps are not slowing down—just the opposite, they are accelerating under extreme competitive pressure.

In Depth:Fast Technology Development

Fast Technology Development

You are facing ever-greater challenges and complexity, and you have unique processes and requirements that demand a unique solution. We work with you to develop a customized tapeout-to-mask flow for your most advanced technology in the shortest time possible. We supply three crucial ingredients to ensure your success:

  • A comprehensive set of compatible tools for every aspect of the tapeout-to-mask flow.
  • Common control languages and flexible interfaces to enable fast and efficient flow integration.
  • Consulting services to adapt our technology to your specific needs in the shortest time possible, and to continue flow optimization as your process reaches maturity.

Calibre® provides all the tools required for an integrated design-to-mask flow:

  • Layout verification and Design-For-Manufacturing (DFM)
  • Mask optical process correction (OPC) and resolution enhancement
  • Dedicated mask writer correction
  • Mask fracturing and mask writer data conversion

Our tool suite is built on a common database and hierarchical geometry processing engine. Our tools are open and accessible through a variety of interfaces, including Calibre database APIs, lithography and metrology APIs, and common rule and control languages.

Mentor Consulting helps customers implement effective design-to-silicon flows to realize higher yield, faster turn-around time, faster time to market, and faster yield ramp. We provide high-quality OPC models and recipes that incorporate production information for the highest accuracy, and customized solution components to increase throughput and flow automation.

This combination of comprehensive tool functionality, flexibility, and Mentor flow engineering support provides you with the fastest and most efficient tapeout-to-mask flow development available.

In Depth:Accurate Resolution Enhancement

Accurate Resolution Enhancement

Calibre nmOPC answers the challenge of low k1 photolithography by delivering several innovations, including:

  • Both sparse and dense simulation (user selectable),
  • Process window optimized OPC,
  • A hybrid computing platform utilizing co-processor acceleration,
  • Compact resist modeling,
  • Design-intent-aware correction algorithms.

Yield-enhancing functions ensure image fidelity across multiple process conditions, providing more robustness and reliability in the manufacturing process.

Our lithographic models have led the way since the 130 nm process node, and are proven in the world’s largest IC manufacturing facilities worldwide. Technology for the 32 nm and 22 nm nodes is already in development, and will be production-proven when your commercial manufacturing ramps up.

John Sturtevant @SPIE 2007

Video: John Sturtevant, Mentor’s Director of RET Technical Support, speaks about the challenges of lithography at advanced IC technology nodes. View Video

Calibre nmMPC

Calibre nmMPC (Mask Process Correction) provides correction specifically developed for e-beam mask writers. Features include…

  • New correction and modeling capabilities improve mask CD linearity and uniformity for advanced nodes, especially for smaller feature sizes (such as SRAFs)
  • Handles long, medium and short range effects with a combination of density-based bias models and variable etch bias (VEB) calibrated models based on physical mask measurements
  • Includes tools for mask model building and customization that are integrated with Calibre Workbench™

Embedded OPC Extends Laser Mask Writers to 65/45nm

Industry Article: Read more details about dedicated mask writer correction from Steffen Schulze, Director of Product Marketing for Calibre MDP and Platform Applications. Read Article

In Depth:Fastest Time-to-Mask

Fastest Time-to-Mask

The Calibre® GDSII-to-Mask solution provides co-processor acceleration based on the Cell/B.E. processor, which has one general purpose and eight numerical processing cores in each physical CPU chip. Calibre software automatically manages task distribution and coordination across a mix of standard x86 and Cell/B.E. platforms connected by a simple Ethernet connection. (Click to view larger)

As the complexity of RET applications for nanometer designs continues to soar, your mask turnaround time (TAT) is growing exponentially. To enable your advanced computational lithography (CL) techniques to run quickly and efficiently, you need a specialized, highly-parallel hardware architecture specifically designed for numerical-intensive problems.

Mentor’s OPC software runs on standard x86 platforms, but offers co-processor acceleration (CPA) as needed by incorporating multicore CPU platforms using the highly parallel Cell Bandwidth Engine (Cell/B.E.) processor. Benefits of CPA include…

  • Provides the computing power needed for fast execution of numerical-intensive algorithms, such as those used for dense simulation
  • Flexibility—with CPA, you select the processing configuration that best meets your specific needs, specifying both the simulation method (sparse or dense modeling) and the target hardware on a mask layer-by-layer basis
  • Supports OASIS to minimize output file size
  • Streamlined algorithms to take advantage of design hierarchy and further improve your TAT, computational efficiency, and throughput compared to flat processing tools

Meeting the Computing Demands of Advanced IC Design

White Paper: Read more about Mentor’s CPA solution. View White Paper

In Depth:Reduce Operational Cost

Reduce Operational Cost

An appropriate mix of commodity x86 and Cell/B.E. computing platforms can increase the performance of the Calibre® RET solution while reducing your overall costs of computing. (Click to view larger)

Mentor’s CPA capability also helps you control operational costs as your computational requirements increase. Achieving the required computational power needed for advanced computational lithography (CL) techniques with standard x86 platforms is prohibitively expensive in terms of hardware, data center footprint, management overhead, power, and cooling. Mentor’s CPA delivers dramatic reductions in hardware, software, and operating costs, while enabling you to incorporate the advanced CL techniques needed for today’s designs.

CPA reduces the number of hardware platforms required, which cuts your data center footprint, management overhead, and power and cooling costs. With CPA, you can cut your total cost of computing in half, when compared to conventional computing hardware alone.

In Depth:Partnership

A Partner You Can Depend On

Success in the GDSII-to-mask flow requires more than a collection of interoperable parts. Besides the best technology available, it requires a partner who can…

  • Help you optimize the entire flow to ensure accuracy, reduce turnaround time, and increase throughput
  • Take you to the next technology node and help you manage the complexity of change—a partner who has done it before

Ultimately your business depends on the competence and dedication of your key technology partners. Mentor has demonstrated time and again that we have the best technology, the most complete solution, and we’re in it for the long haul.

Success Story: Mentor helped Dongbu HiTek reduce their tape-to-mask turnaround time (TAT) by 50% while maintaining consistent manufacturing quality and yield. Read Success Story

More Challenges

Manufacturing Variability Resources

Assessment and comparison of different approaches for mask write time reduction

White Paper: The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout,... View White Paper

Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?

White Paper: Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper

News

View all Manufacturing Variability Resources: White Papers, Datasheets, Web Seminars, and more