Identify Failures with Diagnosis-Driven Yield Analysis

Design, physical verification, DFM, and mask enhancements minimize potential IC failures, and specialized diagnosis tools identify yield-limiting defects during production ramp. With diagnosis-driven yield analysis, you can rapidly narrow down the most likely cause of failures, enabling you to take timely corrective actions in the manufacturing process or changes to the design that impact product yield rates.

Accurate diagnosis allows you to accelerate yield ramp during initial production and improve expected yields for mature products, speeding your time to market and increasing profitability.

With diagnosis-driven yield analysis, you can…

Speed yield ramp by reducing time needed to find root cause of failures

  • Quickly identify probable cause through analysis of volume diagnostics before physical failure analysis

Improve failure diagnosis accuracy

  • Perform high-throughput layout-aware diagnosis of production test data
  • Improve resolution in physical failure analysis

Industry Articles

  • Diagnosis-Driven Yield Analysis
    By Dave Macemon, Mentor Graphics
    Learn how to shorten the path to finding the root cause of yield-limiting systematic defects for advanced IC designs.
  • Yield Learning Flow Provides Faster Production Ramp
    By Dave Macemon, Mentor Graphics
    Find out how diagnosis-driven yield analysis could be taking a new role in the yield learning process to speed yield ramp.
  • Which Way to Yield?
    By Bruce Swanson, Mentor Graphics
    Confused about yield? Bruce Swanson blogs about finding the most direct way to improve yield—failure diagnosis.
  • DFM-Oriented Test Ensures Better Yield
    By Adhir Upadhyay, Vikas Gupta, Mentor Graphics
    Find out how DFM, scan test, and diagnosis can be linked to improve yield.
  • DFT, ATE Drive Yield Improvement
    By Ajay Khoche, Verigy, and Wu Yang, Mentor Graphics
    Find out how advances in automatic test equipment and scan test enable volume diagnosis to reduce the yield-learning effort.

Yield Learning with Tessent Diagnosis and Tessent YieldInsight

Technology Overview: Indentifying the root cause of yield loss can take weeks or months using traditional methods. Learn how using the Tessent yield analysis solutions will significantly shorten this time. View Technology Overview

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis w/DFM

White Paper: This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent... View White Paper

In Depth:Improve Yield Excursion Analysis

Improve Yield Excursion Analysis

During production of a 10-million gate graphics processor chip at the 90 nm technology node, one of our customers had an excursion wafer with 209 defective dies. These dies failed structural logic testing during manufacturing test.

Analysis of the diagnosis results confirmed that a specific open mechanism was the most likely cause of the unexpected yield reduction.

Diagnosis-Driven Yield Analysis Process Flow. (Click to view larger)

  1. Volume diagnosis of the fail logs determined logical failing locations for all of the failing dies.
  2. Design layout information was used to extract layout features likely to lead to interconnect opens if defective.
  3. Diagnosis results and layout features were analyzed to identify and locate the dominant open defect mechanism.
  4. The root cause of the yield excursion was determined to most likely be an abnormality in a process step related to the fabrication of single vias in layer 2.
  5. Physical failure analysis of the defects was done on eight failing dies to validate this conclusion.
  6. A metal deposition step in the manufacturing process was cleaned up to address this problem and improve yield.

Efficiently Performing Yield Enhancements by Identifying Physical Root Cause from Test Fail Data

Industry Article: Read more details of how statistical analysis was applied to logic diagnosis to more efficiently identify the root-cause of a manufacturing yield excursion. View PDF

In Depth:Enhance Yield

Enhance Yield

Diagnosis-driven yield analysis successfully enhanced the yield by 10% for one of our customer’s new system-on-a-chip (SoC) designs.

Layout view of chain diagnosis result

  1. Logic diagnosis was done on 20 scan fails during preproduction, and the results narrowed down the scan chain failures to one suspect that should be either stuck-at-1 or stuck-at-0, a hard defect in silicon.
  2. Three devices were sent to physical failure analysis with a diagnostic report that indicated the suspect scan input path, as well as the scan cell. The results were inconclusive and indicated the defect could be caused by a random issue.
  3. However, using diagnosis-driven yield analysis, the results showed a higher percentage of scan chain failures in the edge of the wafer versus the center.
  4. The exact fault location in the scan chain failing units was isolated. Failure analysis showed poor copper fill, and the process steps were enhanced for all the metal layers.
  5. Scan chain failures were reduced from 13% to 3%, increasing the yield by 10%.

In Depth:Identify Systematic Defects

Identify Systematic Defects to Uncover Hidden
Yield Limiters

The wafer map on the left represents a stacked wafer map for a large number of failing die for one of our customers. Red indicates die locations with higher failure rates, yellow shows medium failure rates, and white, the lower fail rates. Looking at this data, nothing systematic about these failures stands out. A product engineer might likely conclude that they are all random particle defects.

Extracting systematic problems from noise . (Click to view larger)

However, once yield analysis is done and failures corresponding to one specific defect mechanism are mapped, you can now see a systematic problem hidden within the data .

A pattern in the area that is consistently failing indicates an exposure problem on the left side of the reticle. This problem would have been difficult to identify without performing diagnosis-driven yield analysis at the die level.

Archived Web Seminar: This presentation discusses how YieldAssist can provide a new depth of data to empower yield analysis in the nm era and uncover today's hidden systematic defects. View Web Seminar

More Challenges

Manufacturing Variability Resources

Assessment and comparison of different approaches for mask write time reduction

White Paper: The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout,... View White Paper

Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?

White Paper: Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper

News

View all Manufacturing Variability Resources: White Papers, Datasheets, Web Seminars, and more