Ensuring High Yield from the Start

In Depth:Manage Variability

Manage Variability with MCMM

When you use Mentor’s patented MCMM timing kernel to manage manufacturing variability during place and route, you’ll see the payoff in performance, time-to-market, and yield.

Yield, performance, power, timing, and signal integrity are affected in complex ways as ICs grow more sensitive to manufacturing variability, and your bottom line suffers.

You’re faced with reaching design closure for dozens of corner/mode combinations and several power states. You could merge constraints, add margins, or otherwise simplify the problem, but then you risk missing critical consequences of the complex effects of manufacturing variability on your design. For example, variations in resistance due to uneven wire widths or CMP dishing could cause a serious cross-talk problem in one corner/mode combination, but not another. Resizing a buffer to fix the cross-talk violation could then cause a serious DFM violation in another corner/mode scenario. What to do?

Forget about those “typical” strategies. With concurrent MCMM analysis and optimization, you can resolve all of these conflicting requirements during place and route.

Design For Variability White Paper

To learn more about managing variability, download the white paper: “Design For Variability: Managing Design, Process, And Manufacturing Variations In Physical Design”.

In Depth:Improve Yield and Reliability

Improve Yield and Reliability with DFM-Aware Routing

A comprehensive physical design system includes sign-off DRC and DFM capabilities. (Click to view larger)

Lithography distortion is a fact at nanometer nodes. These distortions cause pattern deviations that degrade performance and signal integrity, and lead to manufacturing faults such as bridging, pinching and via failures. Result? Lower yield and reliability that puts you at a competitive disadvantage.

In the past, you could correct for these distortions during mask preparation, but post-layout modifications are no longer enough for your nanometer designs. Push one wire to cure a critical area violation, and you could cause a serious signal integrity violation somewhere else.

Now you can address these complex effects during place and route with Mentor’s 45 nm-ready lithography-driven router with integrated critical area analysis (CAA), CMP and OPC models. Our DFM-aware router gives you an inherently litho-friendly layout with best-in-class routing quality. And, because the optimizations are always MCMM, you can expect robust, full process-window manufacturability.

In Depth:Boost Performance

Boost IC Performance

IC performance determines competitive advantage and pricing. However, you’re losing performance every time you have to over-design or add guardbanding to ensure design closure and high DFM scores.

Concurrent co-optimization of performance and manufacturability throughout place and route lets you reduce guardbanding and get the highest performance from your IC—without sacrificing functional or parametric yield. And deep co-optimization during physical layout won’t delay your design schedule, because Mentor’s multi-threaded, multi-core timing kernel cuts overall design time dramatically, up to 4X on an 8-core machine.

In Depth:Speed to Market

Beat the Competition to Market

Mentor’s Olympus-SoC™ IC implementation system addresses the variability inherent in advanced process node designs. (Click to view larger)

You’ll get faster design closure for even your biggest and most complex designs with Mentor’s place and route tools. Here’s why:

• One-pass timing analysis
  Concurrent, MCMM timing closure means you meet all your metrics, across all corner/mode scenarios, in one pass. Our variability-aware, sign-off quality timing analysis means no late-cycle surprises, and no costly, time-consuming change iterations.
• Faster verification
  Our correct-by-construction router with lithography, CAA, CMP modeling and built-in DRC means drastically fewer DFM violations to fix during physical verification. Faster verification means you reach tape-out faster and launch your products on time.
• High-performance, high-speed platform
  Every step of the place and route flow is multi-threaded and provides almost linear scaling on multicore, multiCPU platforms. Mentor’s timing kernel is the first in the industry to provide true multicore support. Our multicore timer can cut time to design closure by up to 4X when using 8 CPUs.
• Faster Prototyping And Chip Assembly
  Process designs with 100 million+ gates in flat or hierarchical mode. With Olympus SoC, you are never forced to artificially partition designs because of tool capacity limitations, or use less accurate block models during chip assembly.