Playing by the (Design) Rules and Winning the Yield Game
Your job—maximize the performance and reliability of your design. Your challenge—creating the most competitive product that achieves your targeted yield. Where do you start?
To make the best implementation decisions, you need to predict when and where manufacturing variation will impact yield and performance. We’ve been helping designers manage the complexity of design verification for a long, long time, by providing information that helps you focus on the issues that are truly important. We show you exactly which parts of your design are at greatest risk, and help you choose and prioritize fixes. How?
One way is by constantly improving and expanding the capabilities of our existing toolset. Here are just a few of our pioneering techniques for nanometer design:
- equation-based design rule checks,
- advanced device parameter extraction,
- programmable electrical rule checking.
Our model-based and model-assisted verification tools help you predict and avoid manufacturing variability caused by random particles, lithography, CMP, leakage, and device proximity effects.
Calibre: Addressing Nanometer Yield
Mentor Graphics offers a wide range of functionality designed specifically to address the unique challenges of nanometer yield.
The Calibre® nm platform lets you integrate the results from one Calibre tool into the analysis of another, ensuring that your design choices reflect the increasing overlap between variability influences. Calibre’s industry-leading tools and techniques help you push your design’s implementation to its limits, while ensuring manufacturing success.
We also know our tools can’t help you if they don’t contain manufacturing information from the foundry that produces your designs. We work closely with all the major foundries to ensure our tools are calibrated and verified for their processes.
Mentor engineers have been at the forefront of research and innovation at every node, and we’re only increasing our efforts at the nanometer nodes. No matter where your business plans take you, you can bring Calibre with you, knowing that you’ll continue to have the full range of verification tools you need to ensure maximum performance and silicon success.
“Taking actions at the design stage to minimize manufacturing variability is essential to maintaining competitive advantage at advanced process nodes.”
Dr. Fumitomo Matsuoka, Toshiba
“As foundries and EDA vendors work together to accurately model the manufacturing process at advanced nodes, we can have a substantial impact on overall device yield and performance.”
We’ve engineered our Calibre® verification software to specifically address manufacturing variability issues that appear at nanometer nodes, so you can mitigate variability impact during the design verification process. Calibre products maximize the efficiency and accuracy of your design verification process, ensuring you meet your time-to-yield and business goals in a timely and cost-effective manner.
Measure Design Rule Compliance
Accurately Measure Design Rule Compliance
The bottom line is: chips have to work. Design rules were developed to ensure that chips work, but complex technology and smaller process nodes demand tighter spacing and more complex features, two design goals that often conflict. When you’re working in nanometer nodes, you simply can’t measure everything you need to using one-dimensional design rules.
Our unique equation-based design rule checking (eqDRC) lets you replace large linear table-driven rule sets with design rules that use flexible mathematical expressions to accurately capture the multi-dimensional nature of more complex design constructs. With eqDRC, you can write design rules that analyze 3D features and guide you to the implementation that minimizes area while ensuring manufacturability. Plus, you have fewer rules, speeding up your DRC runtimes!
Combining equation-based DRC with traditional DRC allows you to implement nanometer designs with the confidence that they are both DRC-clean and optimized for production and performance.
You’re also faced with trying to implement a foundry’s recommended rules without creating an explosion in both rule file size and design area. How can you optimize the performance of your design while controlling design area and maintaining manufacturability? You need a way to accurately measure the impact of multi-dimensional simultaneous variables and prioritize rule violations so you can make reliable design tradeoffs.
To help you implement recommended rules in a meaningful and efficient way, Calibre YieldAnalyzer incorporates manufacturing models from the foundries to provide automated prioritization of recommended rules violations.
Together, all of these capabilities improve both your design reliability and manufacturability by closing the gaps between design rules and true manufacturing issues.
Optimize Parametric Performance
Optimize Parametric Performance
You have performance goals for your designs, and meeting or missing those goals can be the difference between profit and loss. Shrinking geometries put new and increasing pressure on parametric performance as you try to manage shrinking feature sizes, finer line widths, longer interconnect, more routing layers, and more analog content. Traditional methods of black boxing, assumptive device measurement and gate-level extraction are just not good enough to meet the accuracy requirements of simulating sophisticated IC designs. You need exacting detail – actual device measurement and transistor-level parasitic extraction integrated with lithography simulation – that can provide more accurate transistor models incorporating precise effects that become significant at these smaller nodes.
Calibre LFD™ and Calibre nmLVS together provide you with detailed device parameters based on accurate simulation of the lithographic process window and specific device interactions at very small geometries. You can then plug the resulting device parameters, which reflect actual as-built device shapes, into a SPICE model to produce an accurate timing simulation of how the real device will work. The combination of the Calibre LFD and nmLVS capabilities provides you with a complete and integrated solution that improves your SPICE simulations by providing more accurate results that better reflect actual silicon performance.
Calibre xRC™ lets you extract interconnect parasitics hierarchically, resulting in a compact, hierarchical, transistor-level parasitic data that you can back-annotate and simulate with full-chip circuit simulation tools, such as HSIM. Calibre xRC's resistance and capacitance engines, combined with Calibre nmLVS, let you accurately measure, extract and analyze parasitics and devices accurately, even at the smallest nodes, helping you preserve performance, capacity and yield. Because Calibre xRC gives you greater confidence in your post-layout simulation results, it lets you eliminate prohibitive design margins.
Calibre PERC, the industry’s first programmable ERC tool, enables you to define your own customized electrical checks based on information contained in netlist and layout files. Calibre PERC ensures the highest level of ESD design rule compliance, because it goes beyond traditional layout geometry-based checking to enable verification of specific device and interconnect structures and electrical characteristics. You can even use Calibre PERC to detect electrical rule violations independent of logical design (for example, omission of ESD protection on the schematic or netlist). Using Calibre PERC, you can insert electrical rule checks into your design flow as part of an integrated Calibre platform for cell, block and full-chip verification.
Model Real-World Results Before Production Begins
Model Real-World Results Before Production Begins
As close spacing of layout features increases, the number and severity of random and systematic issues that contribute to manufacturing variability increase. Particle deposition, lithography, CMP, resist stability, and etch process characteristics are just some of the factors that become more challenging to control at nanometer nodes. Tools that incorporate real-world manufacturing models to simulate the impact of these effects on your design enable you to prioritize and minimize a wide spectrum of design limiters to improve design manufacturability.
Calibre LFD™ simulates how a layout will print under a particular lithographic process window, providing information you can use to adjust layouts to improve print quality. Knowing your design is “LFD clean” gives you confidence that you have achieved the higher production quality needed for advanced process nodes.
Calibre LFD’s Design Variability Index scoring lets you compare layout options to determine the layout that will be most robust against manufacturing variation
Calibre YieldAnalyzer integrates random (critical area) and systematic (critical feature) process variability analysis using model-based algorithms that automatically plug layout measurements into yield-related equations to help you identify hot spots – areas of your physical design that have higher sensitivity to variations across the manufacturing process window. To reduce those hot spots in a practical and efficient way, Calibre YieldEnhancer provides you with automated layout enhancements that include built-in functions optimized to maximize coverage and minimize run times. To ensure you maintain design performance, Calibre YieldEnhancer also offers both a net-aware capability and back annotation to the design database.
Thickness variations due to CMP can have a huge impact on nanometer designs. The Calibre planarity solution lets you model the CMP process and automatically add fill to the layout based on layout density, gradient and magnitude assessments. We integrate Calibre CMPAnalyzer and YieldEnhancer capabilities with planarity models based on specific foundry information to allow you to visually review and examine anti-dishing bridge data layer by layer, or for selected areas in your layout. You can also review depth of focus data and identify potential scan band failures and hotspots. We’ve also integrated Calibre extraction tools with Calibre CMPAnalyzer to let you create a comprehensive 3D circuit model with device and interconnect parameters that more closely match silicon results. These results can drive extremely accurate circuit simulations.
Plan for the Future With Confidence
Plan for the Future With Confidence
You understand the importance of adding model-based information into your design verification flow, but you want to know that the information will always be available to you, no matter which node you are working in. You also want tools that can communicate with each other to maximize the integration of information that is critical to success in the smaller nodes.
Model-based and model-assisted Calibre tools use accurate, real-world data to provide the specific guidance and support you need to effectively prioritize and implement those design changes that produce the greatest improvement, based on your business goals.
Mentor Graphics works with all the major foundries to ensure that the models we use are the most accurate available, and we are always planning and working ahead so that when you are ready to move to the next node, you can do so with confidence, knowing that your verification software is ready as well.
Additionally, by using a standard SVRF and TCL-based rules environment across all Calibre applications, we provide you the flexibility to meet the specific and evolving needs of your design teams, while ensuring compatibility with all foundries.
You can rest assured that regardless of the node you design for or the foundry you work with, your Calibre physical verification software will be ready and able to provide you with the same high quality results you expect from Mentor Graphics.