News and Articles
News and Press
- TowerJazz Finds a Unique Solution for Advanced ESD and Power Domain Checking in Calibre PERC
- SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs
- GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC
- Mentor Embedded Continues to Simplify Linux and Open Source Development with Support of the Yocto Project
- Calibre Flow Developed with Mentor Graphics Consulting Boosts GLOBALFOUNDRIES Silicon Yield
- Mentor Graphics Announces PADS Release Targeting Design-for-Manufacturing (DFM) Analysis, High-Speed and Interactive Routing
- Samsung DFM Ready for 20 nm Based on Mentor Graphics Calibre Platform
- IEEE Board of Directors Elevates Janusz Rajski to the Grade of IEEE Fellow
- Mentor Graphics and JEOL to Develop Advanced IC Mask Writing Solutions
- Mentor Graphics Announces Completion of 20 nm Test Chip Tapeout with STMicroelectronics Using Olympus-SoC Place and Route System
- Mentor Graphics and TSMC Address Advanced Node Fill Requirements Using Calibre SmartFill
- Mentor Graphics Vista ESL Platform Takes Center Stage in Mentor’s ESL Strategy with Expanded Functionality
- Mentor Graphics Signs AMDL as New Distributor in India
- Mentor Graphics and GLOBALFOUNDRIES Improve Yield Analysis with Combination of Tessent and Calibre Capabilities
- GLOBALFOUNDRIES and Mentor Graphics Extend Collaboration to Third Generation of DFM
- Mentor Graphics Tessent YieldInsight Demonstrates Faster IC Failure and Yield Analysis at Fujitsu
- Mentor Graphics Introduces Calibre RealTime for Instant Signoff Verification of Custom IC Designs
- MediaTek Adopts Mentor Graphics Calibre PERC as its ESD and Circuit Reliability Verification Solution
- VIA Technologies Adopts Mentor Graphics Calibre PERC for Critical ESD Checking
- Mentor Graphics Calibre PERC Programmable Electrical Rule Checker Improves Fujitsu Chip Reliability
- STARC Advances Test of Low Power ICs Using Mentor Graphics Tessent TestKompress
- Mentor Graphics Completes Test Chip with IC Implementation Flow for Common Platform 32/28nm Technology
- NVIDIA uses Mentor’s Olympus-SoC Place and Route System for Leading-Edge Graphics Processors
- Mentor Graphics Design-to-Silicon Solutions Used in Successful Development of TSMC 28nm Product Qualification Vehicle Test Chip
- Mentor Graphics Calibre Co-Development of TSMC’s iLVS Simplifies Modeling of Advanced Devices for Physical Verification
- SMIC Bases DFM Sign-off Strategy on Mentor Graphics Calibre Platform
- Freescale Semiconductor Collaborates with Mentor Graphics on Tessent Silicon Test, Yield Analysis, Calibre Physical Verification and DFM
- Mentor Graphics Outlines Strategy to Unify Silicon Test and Yield Analysis
- New Mentor Graphics Tessent YieldInsight Product Improves IC Yield through Statistical Analysis of Test Failure Data
- Mentor Graphics Delivers Must-have Reference for the Open Verification Methodology (OVM)
- Trident Microsystems Adopts Mentor Graphics Veloce Hardware Emulator to Accelerate Time-To-Market for their Next Generation Digital TV SoCs
- TSMC Selects Calibre Physical Verification Platform for Integrated Sign-off Flow
- GLOBALFOUNDRIES Selects Mentor Graphics Calibre Platform for Computational Lithography and DFM Enablement
- Mentor Graphics Chairman and CEO to Present Keynote at the PLM Road Map 2009 Conference
- Mentor Graphics and Applied Materials Deploy OASIS.MASK Open Data Standard for Higher Efficiency Mask Manufacturing
- Mentor Graphics Acquires LogicVision; Unites BIST, ATPG and Test Pattern Compression Technologies
- Mentor Graphics Announces Complete Design through Manufacturing Solution in TSMC Reference Flow 10.0
- Mentor Releases New Calibre Versions Using Interoperable iDRC and iLVS Formats Introduced by TSMC
- UMC Qualifies Comprehensive Mentor Graphics Silicon Test Suite for its 65nm and 40nm IC Reference Flows
- Mentor Graphics Announces All-Calibre Physical Verification and DFM Flow for Advanced IC Designs at Fujitsu Microelectronics
- Mentor Graphics Appoints New Vice President of Human Resources
- Mentor Graphics TestKompress ATPG Software Wins Test & Measurement World’s Test of Time Award
- Mentor Graphics Provides Complete 3D Variability Solution Addressing Density and Thickness Challenges
- Cambridge Silicon Radio Limited Successfully Deploys Calibre DFM Solutions to Help Drive Rapid Process Migration
- Mentor Graphics Olympus P&R and Calibre Verification Platforms Qualified for 32nm IC Designs at STMicroelectronics
- Mentor Graphics’ Olympus-SoC Place-and-Route System Wins 2009 DesignVision Award
- Mentor Graphics DFT Tools Adopted by STMicroelectronics for Advanced IC Testing Solutions
- Mentor Graphics and Freescale Expand Collaboration to Improve Manufacturing and Testing of Nanometer Technologies
- Mentor Graphics Olympus-SoC Place-and-Route System Qualifies for TSMC 40nm Processes
- NEC Electronics Selects Mentor Graphics Calibre nmLVS for Advanced Circuit Characterization at 40nm and Below
- Mentor Graphics Olympus-SoC Place-and-Route System Slashes Design Closure Times with Industry’s First Parallel Timing Analysis and Optimization Technology
- TSMC Adopts Mentor Graphics Calibre Equation-Based DRC Feature for Advanced Physical Verification
- IBM and Mentor Graphics to Develop 22nm Computational Lithography Solution for the Integrated Circuit Industry
- Mentor Consulting Slashes Time-to-Mask at Dongbu HiTek with Optimized Calibre Flow
- Mentor Graphics' Calibre nmOPC Product Wins SI Editors’ Choice Best Product Award
- Mentor Graphics Provides Advanced Design For Manufacturing Capabilities in TSMC Reference Flow 9.0
- Mentor Graphics Calibre nmOPC on Cell/B.E. Platform Qualified for Production at IBM
Industry Articles
- Tips for testing processor cores (Apr 6, 2012)
- Dual Approach to Chip Test (Mar 23, 2012)
- Determining the best test patterns for production test - You need to collect data before you can decide on the best test strategy. (Mar 6, 2012)
- Cell-aware ATPG test methods improve test quality (Mar 6, 2012)
- 3D chip design explored by Mentor Graphics (Feb 20, 2012)
- Memory BIST for shared-bus applications (Feb 1, 2012)
- Understanding Cell-Aware ATPG And User-Defined Fault Models (Feb 1, 2012)
- Semiconductor yield improvement with scan diagnosis (Nov 16, 2011)
- Diagnosis-Driven Yield Analysis Improves Mature Yield (Nov 7, 2011)
- Direct diagnosis for compressed ATPG patterns: A successful industrial experiment with layout-aware diagnosis (Oct 19, 2011)
- How to test 3D chips (Sep 21, 2011)
- A New Method to Accelerate the Yield Ramp - 2011 Tech Design Forum (Jul 15, 2011)
Manufacturing Variability Challenges
Design
Mentor’s variability-aware/timing-aware place and route system delivers “correct-by-construction” layouts concurrently optimized for both performance and yield across any number of modes and corners.
Enhance
Mentor’s Calibre® platform provides the fastest, most accurate, and most reliable integrated verification, extraction and design-for-manufacturing (DFM) platform for both library cells and full chips.
Fabricate
Mentor’s fast, accurate, and cost-effective mask resolution enhancement and data prep flows ensure quick mask turnaround and high manufacturability at 65 nm, 45 nm, 32 nm and beyond.
Ramp
Mentor’s production yield solution combines the power of diagnosis-driven yield analysis and high-quality manufacturing test to accelerate yield ramp.
Manufacturing Variability Resources
Assessment and comparison of different approaches for mask write time reduction
White Paper: The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout,... View White Paper
Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?
White Paper: Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper
News
- TowerJazz Finds a Unique Solution for Advanced ESD and Power Domain Checking in Calibre PERC
- SMIC Employs Mentor Graphics Calibre PERC for Reliability Verification of Multi-Power Domain SoCs
- GLOBALFOUNDRIES Improves IC Reliability with Customized Circuit Checks Using Mentor Graphics Calibre PERC
- Mentor Embedded Continues to Simplify Linux and Open Source Development with Support of the Yocto Project
View all Manufacturing Variability Resources: White Papers, Datasheets, Web Seminars, and more