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Mentor Graphics Questa Verification Platform Adds Software-Driven Verification for Multi-Core SoC Designs

For more information contact

Carole Dunn
carole_dunn@mentor.com
Mentor Graphics
503-685-4716

Sonia Harrison
sonia_harrison@mentor.com
Mentor Graphics
503.685.1165

WILSONVILLE, Ore., July 15, 2013 — Mentor Graphics Corp. (NASDAQ: MENT) today announced that intelligent software-driven verification (iSDV) has been added to the Questa® functional verification platform to automatically generate embedded C test programs for both single-core and multi-core SoC design verification. As a result, engineering teams find more system level design bugs earlier in the verification process—during simulation or emulation, when they are easier and more cost effective to debug—before they escape into the prototype lab.

“To fully verify our high performance SoC bus fabric subsystems, we have to generate all kinds of complex traffic scenarios. Using Questa’s intelligent testbench automation we are able to achieve all of our performance and functional verification goals while shaving time off our schedule,” said Galen Blake, Altera senior verification architect. “With Questa iSDV we can run embedded C test programs with RTL level testbenches allowing us to fully verify our system under stressful, but realistic, operational conditions, giving us the highest degree of confidence.”

The Questa iSDV technology addresses a common challenge encountered by many engineering teams verifying multi-core SoC designs. As processors, memory, interconnect and peripherals are assembled, creating system level test programs is complex and time-consuming. Manually writing directed tests in C is not scalable, and constrained random testing in C is not practical. As a result, most verification teams jump straight to hardware/software co-verification or worse yet, to the prototype lab, missing a critical phase of verification.

“Writing embedded test programs manually is difficult, but jumping from a handful of tests straight to booting an OS, loading drivers and running software applications is like going from the desert to drinking from a fire hose,” said Mark Olen, verification solutions technologist, Mentor. “Questa iSDV bridges the gap between IP block and full system level verification by successfully applying intelligent testbench automation at the system level.”

While writing directed tests in C to verify single-core designs at the system level is challenging, today’s multi-core, multi-threaded designs have made this process virtually impossible. Questa iSDV automates this process, creating embedded test programs that run in either the Questa verification or Veloce® emulation environments offering scalability across engines.

Product Availability

The Questa iSDV tool is available immediately as part of the Questa functional verification platform. For product information, contact your Mentor Graphics sales representative, call 800-547-3000 or visit the website at http://www.mentor.com/products/fv/.

(Mentor Graphics, Questa and Veloce are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.)

About Mentor Graphics

Mentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

 
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