Calibre DFM

Reducing Random Particle Defects

Random particle defects are a fact of IC manufacturing, but the number and severity of these defects increases as layout features and the space between them continue to shrink. Calibre helps you identify and eliminate susceptible areas in your design.

Recommended design rules use manufacturing information to suggest spacing's that reduce the overall chances of random particle defects. However, recommended rules can generate thousands of rule violations, with no information to help you decide which ones are most critical. Calibre YieldAnalyzer’s critical area analysis (CAA) uses manufacturing information about the process’ particle sizes and probability distribution to identify specific areas of an integrated circuit layout with a higher than average vulnerability to random particle defects. Using recommended rules and Calibre YieldAnalyzer together, you can prioritize design adjustments to minimize the chances of shorts or opens in the manufactured chip while maintaining tapeout schedules.

Calibre YieldAnalyzer performs CAA on all base and interconnect layers of a design, prioritizing violations using a weighted scale to identify specific features with the highest sensitivity to random particles. It provides graphs and reports that give you the means to assess layout improvement trade-offs . Calibre YieldAnalyzer lets you focus on the areas that will have the most impact, which improves both productivity and yield.

Minimizing Process Variation Defects

Calibre YieldAnalyzer also performs critical feature analysis (CFA), a flexible extension to traditional recommended rules analysis. Calibre YieldAnalyzer employs a model-based approach that automatically plugs layout measurements into yield-related equations, using process-specific information supplied by the foundry to identify areas of a physical design that have higher sensitivity to variations across the manufacturing process window. CFA analysis identifies potential “hot spots” due to a variety of systematic variability issues, including lithography, CMP, resist stability, and etch process characteristics.

You can then view the results in charts and graphs that allow you to quickly hone in on problematic features. Calibre YieldAnalyzer provides specific guidance to help you quickly locate and prioritize these hot spots and determine what layout changes will result in the greatest improvement.

Reducing Lithography Variation

Calibre LFD™ helps you create a “litho-friendly” design by simulating how a layout will print under a particular lithographic process window, providing information you can use to adjust layouts to improve print quality. Calibre LFD allows you to achieve an “LFD clean” as well as a “DRC clean” sign-off to ensure higher production quality for advanced process nodes.

Calibre LFD analysis can be used in conjunction with place and route tools to prevent “litho-unfriendly” patterns from being created during layout, or in combination with DRC to identify potential layout “hot spots” that may require adjustments to improve image fidelity during production.

Reducing Planarity Variation

The impact of chemical mechanical polishing (CMP) is inherently pattern-dependent. Whether a feature is isolated or located in a dense array affects both polishing time and results. Likewise, circuit performance is also affected by how the physical layout reacts to CMP. Controlling both thickness and capacitance variation is a balancing act.

Calibre’s model-based planarity flow integrates Calibre CMPAnalyzer and Calibre YieldEnhancer capabilities to help you reduce metal thickness variation and improve both functional and parametric yield.

As a standalone capability, the SmartFill function of Calibre YieldEnhancer allows you to automatically add fill elements directly into your layout based on design density. However, when you need even more precision, you can use Calibre CMPAnalyzer to determine an optimum filling strategy based on layout density, density gradient, and magnitude assessments. This intelligent “model-based fill” approach provides optimum planarity improvement to reduce bridging due to dishing and thickness variations, while minimizing added parasitic capacitance and its impact on timing.

Using Calibre CMPAnalyzer in conjunction with a CMP simulator, you can also highlight and view specific planarity problems within designs. Calibre CMPAnalyzer allows you to visually review and examine anti-dishing bridge data layer by layer, or for selected areas in your layout.

Accurate prediction of the parametric implications of CMP requires knowledge of CMP process variation, design-specific considerations, and the impact of metal fill added to designs. Thickness values generated by Calibre CMPAnalyzer also can be fed into the Calibre xRC™ tool for more accurate parasitic extraction. Used together, Calibre tools help you create a comprehensive 3D circuit model with device and interconnect parameters that more closely match silicon results and drive extremely accurate circuit simulations.

The Calibre Advantage

All Calibre family products run on the fully-integrated Calibre hierarchical geometry engine, are compatible with the OASIS® database format, and employ a unified command language, uniquely enabling a fully-integrated design to mask flow.

By integrating random and systematic process analysis with accurate foundry process models, the Calibre nm Platform not only accounts for the combined impact of these effects on design manufacturability, but enables you to prioritize and guide manufacturability improvement in light of a wide spectrum of yield limiters.

As we move beyond 65nm, tight linkages between EDA tools and manufacturing processes become more and more critical. Model-based verification, analysis, and visualization guide you to the errors that truly impact performance and yield, allowing you to focus your time and attention where it provides the greatest return. With Calibre’s full range of design for manufacturing tools, the Calibre physical verification platform provides a comprehensive approach to yield management at advanced process nodes.