Olympus-SoC Place and Route
Manufacturing-Aware Physical Implementation
Olympus-SoC™ is a sophisticated, manufacturing-aware physical implementation system designed for the rigorous place and route requirements of today’s nanometer designs. Built on a patented multi-CPU, MCMM timing kernel, Olympus SoC provides concurrent analysis of critical design metrics such as timing, power, area, signal integrity and lithography across all corner/mode scenarios.
Olympus-SoC fully understands systematic variability and integrates powerful DFM functions seamlessly. Features such as variability-aware MCMM optimization, litho-driven routing, and concurrent co-optimization of all closure criteria (including DRC/DFM, timing, power, signal integrity, performance, and area) ensure your layout is highly manufacturable.
Olympus-SoC’s advanced software architecture is inherently scalable, and includes both an extremely efficient graph representation for timing information and a very concise memory footprint.
All Olympus-SoC capabilities are built on a Multicorner-multimode timing kernel.
DFM capabilities are built in to the Olympus-SoC 45 nm-ready router, so tasks you once had to perform as post-processing steps, like double via insertion, cell swapping, wire widening, and wire spacing, are now completed automatically during route optimization to provide you with a “correct-by-construction” implementation.
What Olympus-SoC provides you:
- Better IC performance
Incorporate variability models from your fab with other libraries and constraints for concurrent optimization across any number of MCMM scenarios. - Improved yield
Address manufacturability in a timing context during implementation using correct-by-construction, litho-driven routing. - Faster closure
Radically reduce your design iterations with concurrent co-optimization of all closure criteria across all corner/mode scenarios. Shorten your design time with incremental extraction and multi-threaded, multi-CPU engines. - Flexible design flow, easy tool adoption
Simplify your design flow with a physical design solution that accepts all standard industry formats, has a full Tcl scripting interface, and a flexible API. Olympus-SoC easily plugs into your existing methodologies. DRC/DFM capabilities are built into the flow, becoming virtually transparent to the user.
The Olympus-SoC flow is based on the MCMM timing core, and is fully multi-threaded for parallel execution in every step of the flow, including timing analysis and optimization. (Click to view larger)
Olympus-SoC
Advanced multi-corner, multi-mode, (MCMM) technology and lithography-driven routing. Learn more about Olympus-SoC
Resources
Olympus-SoC Overview
Technology Overview: The Olympus-SoC™ Design for Variability IC implementation solution is purpose-built to address the performance, capacity, time-to-market, and variability challenges at advanced nodes. With full support... View Technology Overview
Foundry Resources
Mask data preparation flow for advanced technology nodes
White Paper: The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes.... View White Paper
Roadmap to sub-nanometer OPC model accuracy
White Paper: OPC models describe the entire patterning process, including photomask, optics, resist, and etch as a set of separately characterized modules. It is difficult, however, to definitively calibrate the optics... View White Paper