Olympus-SoC Place and Route

Olympus-SoC fully understands systematic variability and integrates powerful DFM functions seamlessly. Features such as variability-aware MCMM optimization, litho-driven routing, and concurrent co-optimization of all closure criteria (including DRC/DFM, timing, power, signal integrity, performance, and area) ensure your layout is highly manufacturable.

Olympus-SoC’s advanced software architecture is inherently scalable, and includes both an extremely efficient graph representation for timing information and a very concise memory footprint.

DFM capabilities are built in to the Olympus-SoC 45 nm-ready router, so tasks you once had to perform as post-processing steps, like double via insertion, cell swapping, wire widening, and wire spacing, are now completed automatically during route optimization to provide you with a “correct-by-construction” implementation.

What Olympus-SoC provides you:

• Better IC performance
  Incorporate variability models from your fab with other libraries and constraints for concurrent optimization across any number of MCMM scenarios.
• Improved yield
  Address manufacturability in a timing context during implementation using correct-by-construction, litho-driven routing.
• Faster closure
  Radically reduce your design iterations with concurrent co-optimization of all closure criteria across all corner/mode scenarios. Shorten your design time with incremental extraction and multi-threaded, multi-CPU engines.
• Flexible design flow, easy tool adoption
  Simplify your design flow with a physical design solution that accepts all standard industry formats, has a full Tcl scripting interface, and a flexible API. Olympus-SoC easily plugs into your existing methodologies. DRC/DFM capabilities are built into the flow, becoming virtually transparent to the user.