Olympus-SoC Place and Route

Manufacturing-Aware Physical Implementation

Olympus-SoC™ is a sophisticated, manufacturing-aware physical implementation system designed for the rigorous place and route requirements of today’s nanometer designs. Built on a patented multi-CPU, MCMM timing kernel, Olympus SoC provides concurrent analysis of critical design metrics such as timing, power, area, signal integrity and lithography across all corner/mode scenarios.

Olympus-SoC fully understands systematic variability and integrates powerful DFM functions seamlessly. Features such as variability-aware MCMM optimization, litho-driven routing, and concurrent co-optimization of all closure criteria (including DRC/DFM, timing, power, signal integrity, performance, and area) ensure your layout is highly manufacturable.

Olympus-SoC’s advanced software architecture is inherently scalable, and includes both an extremely efficient graph representation for timing information and a very concise memory footprint.

All Olympus-SoC capabilities are built on a Multicorner-multimode timing kernel.

DFM capabilities are built in to the Olympus-SoC 45 nm-ready router, so tasks you once had to perform as post-processing steps, like double via insertion, cell swapping, wire widening, and wire spacing, are now completed automatically during route optimization to provide you with a “correct-by-construction” implementation.

What Olympus-SoC provides you:

  • Better IC performance
    Incorporate variability models from your fab with other libraries and constraints for concurrent optimization across any number of MCMM scenarios.
  • Improved yield
    Address manufacturability in a timing context during implementation using correct-by-construction, litho-driven routing.
  • Faster closure
    Radically reduce your design iterations with concurrent co-optimization of all closure criteria across all corner/mode scenarios. Shorten your design time with incremental extraction and multi-threaded, multi-CPU engines.
  • Flexible design flow, easy tool adoption
    Simplify your design flow with a physical design solution that accepts all standard industry formats, has a full Tcl scripting interface, and a flexible API. Olympus-SoC easily plugs into your existing methodologies. DRC/DFM capabilities are built into the flow, becoming virtually transparent to the user.

The Olympus-SoC flow is based on the MCMM timing core, and is fully multi-threaded for parallel execution in every step of the flow, including timing analysis and optimization. (Click to view larger)

Olympus-SoC

Advanced multi-corner, multi-mode, (MCMM) technology and lithography-driven routing. Learn more about Olympus-SoC

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Manufacturing Variability Challenges

Design

Mentor’s variability-aware/timing-aware place and route system delivers “correct-by-construction” layouts concurrently optimized for both performance and yield across any number of modes and corners.

Enhance

Mentor’s Calibre® platform provides the fastest, most accurate, and most reliable integrated verification, extraction and design-for-manufacturing (DFM) platform for both library cells and full chips.

Fabricate

Mentor’s fast, accurate, and cost-effective mask resolution enhancement and data prep flows ensure quick mask turnaround and high manufacturability at 65 nm, 45 nm, 32 nm and beyond.

Ramp

Mentor’s production yield solution combines the power of diagnosis-driven yield analysis and high-quality manufacturing test to accelerate yield ramp.

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