Silicon Test and Yield Analysis
Diagnosis-Driven Yield Analysis — Faster Track to Root Cause and Improved Yield
ICs developed at advanced technology nodes of 65 nm and below exhibit an increased sensitivity to small manufacturing variations. New design-specific and feature-sensitive failure mechanisms are on the rise. Complex variability issues that involve interactions between process and layout features can mask systematic yield issues. Without improved yield analysis methods, time-to-volume is delayed, mature yield is suboptimal, and product quality may suffer, thereby threatening your product’s profitability.
Tessent YieldInsight
Tessent® YieldInsight™ statistically analyzes diagnosis data to identify and separate systematic yield limiters before any failure analysis is done.
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Featured Conference Papers
ASMC Conference 2012: How GLOBALFOUNDRIES and Mentor Graphics used layout-aware scan diagnosis to uniquely identify systematic critical features to ramp the GF 28nm yield. Download PDF
ISTFA Conference 2011: Layout-Aware Diagnosis Leads to Efficient and Effective Physical Failure Analysis TSMC, AMD and Mentor Graphics utilize layout-aware diagnosis to increase the efficiency of Physical Failure Analysis Download PDF
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Diagnosis-driven yield analysis is a methodology that uses production test results, volume scan diagnosis, and statistical analysis to identify the cause of yield loss before any physical failure analysis is done. This methodology can reduce the root cause cycle time 75-90%.
The diagnosis-driven yield analysis solution from Mentor Graphics combines the automated diagnosis capabilities in Tessent® Diagnosis with advanced statistical analysis and data mining provided by Tessent YieldInsight™. Leveraging manufacturing test results and design data, this solution enables IC manufacturers to identify the probable cause of yield loss. This solution significantly reduces the time it takes to identify the root cause of yield loss and identifies yield limiters that may otherwise go unnoticed.
Resources
Foundry Resources
Mask data preparation flow for advanced technology nodes
White Paper: The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes.... View White Paper
Roadmap to sub-nanometer OPC model accuracy
White Paper: OPC models describe the entire patterning process, including photomask, optics, resist, and etch as a set of separately characterized modules. It is difficult, however, to definitively calibrate the optics... View White Paper