Unique Challenges of Nanometer
Mentor Graphics recognizes the unique challenges you face at the nanometer process nodes. Our verification products have been reengineered to specifically address these issues so you can recognize and mitigate their impact before tapeout. Even before you apply the advantage of model-based design tools, Calibre® products help you maximize the efficiency and accuracy of the design process for advanced nodes.
Enhanced Design Rule Coverage
Traditional physical verification relies exclusively on simple one-dimensional design rule checks to identify sensitive layout features that are likely to fail during manufacturing. The number and complexity of these design rule checks are expanding dramatically, due to increased manufacturing variability at advanced nodes, and the increasing sensitivity of manufacturing to a variety of complex design features. Certain required checks are extremely difficult to implement using traditional DRC approaches that require coding large tables of measurement thresholds, while multi-variate and/or 2D/3D interactions are impossible to define. Designers often attempt to deal with these limitations by making their checks more granular, sacrificing accuracy.
A new technique, known as Equation-Based DRC (eqDRC), has been developed to span the gap between traditional DRC and specialized DFM process simulators by bringing user extensibility and traditional DRC-like run times to a whole host of new design/process interactions. A part of Calibre nmDRC, eqDRC extends traditional DRC to define clustered multi-dimensional design feature measurements with flexible mathematical expressions, giving the designer a customizable physical modeling tool and enabling the analysis of complex interactions that could not previously be verified through traditional design rules.
eqDRC can provide a wide array of value to many groups across the design flow:
- eqDRC allows design teams to reduce cell/design area by reducing the amount of over-constraint applied to design features. In addition, manufacturing yield is improved by closing the gaps between traditional design rule checks and real-world manufacturing issues.
- eqDRC simplifies the coding of advanced checks and reduces the rule deck size.
- eqDRC increases engineer debug productivity and reduces debug time by reducing the number of rules to be checked. Because eqDRC enables the designers to “reverse” an equation and solve for specific variables to determine the impact on yield, they can now understand with a high degree of accuracy how changing a specific variable (e.g., a polygon) by a specific amount can solve or reduce yield issues.
- eqDRC provides the ability to use equations that accurately describe the underlying manufacturing issues. It also reduces “escapes” from the intent of the DRM. Foundries can express actual process variation metrics as a function of multi-dimensional design variations to prioritize and flag potential issues in ways that were never before possible. These continuous, multi-dimensional functions (equations) eliminate the need for threshold tables entirely. As a result, checks are easier to specify, easier to debug, and are potentially more accurate. As new process or design requirements are identified, both the foundry and the designer can create new equations or modify existing equations to maintain yield and performance goals.
Using eqDRC in conjunction with traditional DRC enables designers to perform design checks that are not feasible with one-dimensional design rules alone. Some of these checks could be related to DFM initiatives, while others might be unique to a customer’s specific process or design objectives. eqDRC gives designers a straightforward way to introduce new physical design checks that can increase the yield of a manufacturing process, or ensure specific performance qualities, such as low leakage, that a customer may desire. Not only that, eqDRC provides these additional capabilities without increasing the difficulty and overhead of creating and maintaining DRC decks, and without DRC runtime performance penalties.
Advanced Device Parameter Extraction
At 45 nm and below, companies need an advanced systematic device extraction flow integrated with their lithography flow that can provide more accurate transistor models incorporating precise effects that become significant at these smaller nodes. Calibre nmLVS provides detailed device parameters based on accurate simulation of the lithographic process window and specific device interactions at very small geometries. In tandem with Calibre LFD™ (Litho-Friendly Design), the Calibre nmLVS ADP (Advanced Device Parameter) features allow critical device dimensions to be extracted from the LFD-modeled contour geometries to determine a set of equivalent effective dimensions for the devices. The resulting device parameters, which reflect actual as-built device shapes, can then be plugged into a SPICE model to produce an accurate timing simulation of how the real device will work. For drawn parameters, the Calibre nmLVS component is compliant with the latest industry standard models and includes foundry-specific models for handling advanced stress effects. The combination of the Calibre LFD and nmLVS capabilities provides a complete and integrated solution that improves SPICE simulations by providing more accurate results that better reflect actual silicon performance.
Improved Signal Integrity and Timing Closure
The shrinking geometries of nanometer designs have revealed significant concerns over signal integrity and timing closure. Serious challenges are confronting designers that have profound impact upon the success of today's sophisticated analog mixed-signal (AMS) designs. These challenges stem from a combination of factors that emerge in nanometer scale design, such as shrinking feature sizes, finer line widths, longer interconnect, more routing layers, and more analog content. Traditional methods of black boxing, assumptive device measurement and gate-level extraction are not sufficient to meet the accuracy requirements of simulating sophisticated IC designs. This is a task that requires exacting detail – actual device measurement and transistor-level parasitic extraction – evaluated across the characteristics of the entire design.
Calibre® xRC™ delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation. Calibre xRC is able to extract interconnect parasitics hierarchically, resulting in a compact, hierarchical, transistor-level parasitic data that can be back-annotated and simulated with full-chip circuit simulation tools, such as HSIM. By using hierarchical storage and leveraging the circuit hierarchy and isomorphism during simulation, Calibre xRC and HSIM achieve breakthrough performance for very large circuits, while delivering detailed SPICE-level accuracy.
Nanometer effects can cause an entire chip to fail, and must be correctly accounted for in post-layout simulation and analysis to ensure acceptable yield. Calibre xRC's new resistance and capacitance engines, combined with Calibre LVS, fully comprehend the boundary of the BSIM4.0 simulation model to accurately measure, extract and analyze these new parasitics in a geometrically accurate way with smaller netlists, helping to preserve performance, capacity and yield.
Calibre xRC's resistance engine provides accurate fracturing, including precise width and resistor location for electromigration analysis. It also offers enabling technologies for inductance extraction and improved device pin handling, improved gate pin placement and user control over gate region extraction. Additionally, the algorithms are hierarchical and efficient, ensuring high accuracy while maintaining performance and capacity.
Calibre xRC's capacitance engine delivers a tight correlation to field solver and silicon data, greatly improving overall accuracy of results. In addition, it incorporates special models for vias, contacts and the poly-to-contact area, as these are quite susceptible to significant and elusive capacitance effects. Because Calibre xRC gives designers greater confidence in their post-layout simulation results, it eliminates prohibitive design margins.
Customizable Electrical Rule Checks
Electrostatic discharge, advanced electrical rule checking, and multiple power domains are top issues on a long list of complex geometrical and electrical verification requirements that are difficult to check with standard verification tools. Mentor Graphics developed Calibre PERC to allow you to specifically address these issues, as well as the reliability challenges that arise during the circuit and electrical verification process.
Calibre PERC is the industry’s first programmable ERC tool, allowing customers to define their own customized checks based on information contained in netlist and layout files. One critical application of Calibre PERC is to verify the completeness of circuitry needed to protect a device against electrostatic discharge (ESD), which can cause catastrophic device failures in manufacturing, leave devices susceptible to damage during shipping and assembly, or decrease device life in the field. Calibre PERC ensures the highest level of ESD design rule compliance because it goes beyond traditional layout geometry-based checking to enable verification of specific device and interconnect structures and electrical characteristics. It can be used to detect electrical rule violations independent of logical design, for example, omission of ESD protection on the schematic or netlist.
Calibre PERC can be used in combination with Calibre nmLVS to find design errors. Errant signal paths, and other soft connection errors not readily identified by traditional tools. Users can run multiple electrical rule checks independently or together, using either standard rules from the foundry, or their own unique custom rules. Using Calibre PERC as part of an integrated Calibre platform, users can easily insert electrical rule checks into their design flow for cell, block and full-chip verification. Employing standard SVRF and TCL-based rules environment across all applications provides customers the flexibility to meet the specific and evolving needs of their design teams, while ensuring compatibility with all foundries.
Event: Learn how to leverage the superior performance and capacity of the Calibre design-to-silicon platform, a comprehensive suite of tools designed to address the complex handoff between design and manufacturing. View Event
Technology Overview: Calibre PERC is a reliability verification platform, providing robust, full chip, sign-off quality checks in an integrated environment. From your first schematic, through SoC assembly, to the final layout,... View Technology Overview
Technology Overview: Calibre® nmDRC addresses the physical verification challenges of nanometer designs with a new Hyperscaling architecture that provides best-in-class DRC run times with scalability to 100 CPUs. View Technology Overview
White Paper: The trend to reduce critical features dimension has dramatically increased design file size. Design tape–out flows at the 28 nm technology node handle post-OPC data files that reach hundreds of gigabytes.... View White Paper
White Paper: OPC models describe the entire patterning process, including photomask, optics, resist, and etch as a set of separately characterized modules. It is difficult, however, to definitively calibrate the optics... View White Paper