Mentor Consulting Slashes Time-to-Mask at Dongbu HiTek with Optimized Calibre Flow
Mentor Graphics' consulting division successfully completed an engagement at Dongbu HiTek, resulting in a 50 percent reduction in tape-to-mask turnaround time (TAT) while maintaining consistent manufacturing quality and yield. The improvements were achieved by optimizing Dongbu HiTek’s overall RET/MDP flow and taking advantage of the newest capabilities of the Calibre® OPC and Calibre OPCverify™ software solutions for lithography process simulation and correction.
“We place emphasis on finishing our tasks on time and within budget, and on sharing knowledge with our customers regarding how the improvements were accomplished and what further optimizations might be possible in the future.”
According to Dr. Jae Song, executive vice president of marketing at Dongbu HiTek, “We’re very happy with the results of our partnership with Mentor Consulting. The results of this engagement have enabled Dongbu HiTek to substantially accelerate time-to- mass production for its customers. For example, we can accomplish the OPC flow for a 110 nanometer multi project wafer in two days compared to ten days before this engagement. For a chip requiring several respins, faster OPC TAT can accelerate mass production by more than 30 days. Mentor Consulting completed the engagement on time, and the OPC TAT improvements of 50 to 80 percent exceeded our expectations.”
Dongbu HiTek, headquartered in Seoul, Korea, provides wafer processing supported by comprehensive design support (IP and design libraries), prototype development and verification, and packaging and module development that add high value to display and various mobile applications.
The four month project, which started in March 2008 performed by consultants from Mentor's Cairo Office and Dongbu HiTek’s OPC engineers, included migrating Dongbu HiTek to the latest release of the Calibre OPC and OPCverify products to take full advantage of new tool capabilities. Mentor Consulting also implemented its RET/MDP optimization methodology to improve Dongbu HiTek’s overall RET/MDP flow to achieve faster turnaround while maintaining accurate OPC models and recipes, validated by mask quality and pattern fidelity measurements. During the engagement, Mentor Consulting also transferred best practices for achieving optimal flow performance to the Dongbu HiTek team to enable them to make future optimizations and to adapt to evolving process requirements.
“Mentor Graphics operates on the ‘partnership principle,’ providing both technologies and methodologies tailored to the needs of our customers,” said Paul Hofstadler, vice president of Worldwide Consulting at Mentor Graphics. “We place emphasis on finishing our tasks on time and within budget, and on sharing knowledge with our customers regarding how the improvements were accomplished and what further optimizations might be possible in the future. We are already providing services below 32nm, so Mentor Consulting is our customers’ preferred choice when they are ready to move to the next technology node, or to optimize their existing tape-to-mask flow.”
Atmel increases yield while reducing time-to-market and design costs with Mentor Graphics Calibre® nmDRC, LVS and xRC™.
When Atmel faced increasing delays and mounting costs in the verification and production of nanometer designs, they turned to Calibre products from Mentor Graphics for the solution
Atmel Corporation, founded in 1984, is one of the elite Integrated Device Manufacturer (IDM) companies capable of integrating dense nonvolatile memory, logic and analog functions on a single chip. Like any IDM, Atmel’s success depends both on time-to-tapeout and chip performance, two opposing forces in the world of chip design. This tug-of-war becomes even more vigorous as companies move into smaller design geometries and their production, particularly in memory design. The sheer complexity and density of nanometer designs can easily overwhelm many of the verification solutions available, making full chip design testing and verification only a pipe dream. Layout variations and unintended interactions can degrade chip performance and decrease yield, but the lack of adequate testing capability often means these issues go undetected until mask generation and silicon prototyping, an expensive way to debug.
Atmel constantly investigates ways to decrease the time needed to get a large memory design to market while ensuring good yields. If they can produce chips faster and reach their yield targets more quickly, they can access the market earlier and at a lower cost point, while delivering the promised performance.
As Atmel progressed to smaller design geometries, problems began to affect their chip production. Their most critical need was to reduce the number of silicon spins needed to achieve yield and performance targets. Their dense memory designs, some including memory cores in excess of 2GB, could not be fully or adequately tested with their current tool set. Core/periphery interface errors that remained undetected during DRC and LVS were coming to light only after mask generation and silicon prototyping, both hugely expensive and time-consuming processes which then had to be repeated after redesign, often multiple times, endangering Atmel’s delivery schedules, reputation and profits.
Finding a Solution
Atmel identified the following criteria for solution analysis:
- They needed DRC and LVS products that could handle the full chip design
- They needed the ability to extract a hierarchical parasitic netlist to feed the hierarchical simulators
- They needed the ability to perform hierarchical checking across the full chip design (core and periphery)
- They wanted to standardize on one tool set across their internal organizations to simplify the verification flow and eliminate discrepancies between core analysis and full-chip analysis
- They wanted a tool set that they could easily integrate with their existing design and simulation environments
After a thorough consideration of the available options, Atmel selected the Mentor Graphics Calibre nmDRC, LVS and xRC products to deliver the performance, testing and extraction flow capabilities they needed to meet their performance and delivery targets. Calibre’s unique geometric processing engine, which underlies each of the Calibre verification products, ensures Atmel of the full-chip extraction and simulation capabilities they need, coupled with the fast runtimes that they require. Additionally, Calibre output is typically more accurate than that of other verification products, due to the dedicated syntaxes used by Calibre, and Calibre debugging is simplified through the use of hierarchical error identification.
But for Atmel, the greatest value of Calibre lay in the savings in mask generation and silicon prototyping. Prior to Calibre implementation, Atmel was blackboxing the core, because their tools did not have the capacity to handle a full-chip design. This led to mask and silicon failures caused by undetected core/periphery interface errors. Eliminating this weakness in the production process provides a significant leap in productivity for Atmel.
Now, with the Calibre products’ full-chip extraction and simulation capabilities, coupled with their fast runtimes, Atmel can find and eliminate performance issues prior to mask generation. Not only are they cutting their time-tomarket by a factor of 5-10x, they are also saving hundreds of thousands, if not millions, in otherwise wasted mask and silicon creation costs.
- Ability to check the full design in context, eliminating silicon failures before mask generation
- Ability to run core and full-chip analyses using the same software, ensuring integrity of results
- Ability to do full-chip extraction and simulation with xRC to HSim flow, providing greater confidence in ability to meet timing expectations
And the benefits? Of course, Atmel is saving significant money and reducing their time-to-market by reducing iterations in mask production and silicon prototyping. But they’re also enjoying a few other advantages:
- Improved error checking (esp. on core/periphery errors), leading to decreased time to yields
- Faster debugging, providing more time to find and fix design issues impacting yield
- Reduced turnaround times, allowing more time for multiple iterations
- Reduced time-to-tapeout while still meeting performance specifications
- Increased productivity of design team
Although Atmel expected to gain new performance capabilities and increased speed, they were still pleasantly surprised with the actual functionality and flexibility of the Calibre products. One bonus they hadn’t considered was the added disk space they gained as a result of the processing efficiency of the Calibre engine.
Now add to that the support time and costs being saved through the rapid response of Mentor Graphics’ awardwinning technical support and consulting services, and Atmel is delighted with the results of their Calibre usage. So much so, that they are now considering ways to standardize on Calibre in other areas.
After completing two tapeouts using the Calibre products, Atmel believes they have found the best solution to their previous design roadblocks. “Calibre gives us the capability and flexibility we need to speed up our process. We’ve been able to reduce our time-to-tapeout while improving our ramp to yield,” said Edward Hui, Director of the Flash Group at Atmel Corporation.
Not only did Atmel achieve the capacity and performance they were hoping for, but they also exceeded their expectations for value and return on investment. That sort of result is exactly what Mentor Graphics was anticipating.
“Mentor Graphics strives to provide every customer with the very best in functionality and performance,” stated Anthony Nicoli, Director of Marketing for Calibre Physical Verification and Extraction at Mentor Graphics. “Atmel’s success is our success, and it only reinforces our determination to continue providing innovative solutions and products for IC design and manufacturing.”
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