Technical Leadership

Addressing Advanced Process Nodes

The Mentor Graphics Design-to-Silicon Solution for Managing Variability incorporates many unique technologies developed specifically to address issues that arise at advanced process nodes. There is no silver bullet or single-point solution for variability. It takes innovation at every stage of the IC implementation flow.

Digital IC Physical Design (Place and Route)

  • Multi-corner Multi-mode
    The Olympus-SoC™ system leads the place and route pack with true multi-corner multi-mode (MCMM) analysis and optimization throughout the physical design flow. Our patented method for storing multiple timing graphs as a single representation allows all place-and-route engines and APIs to incorporate MCMM capabilities.
  • DFM-Aware Routing
    Olympus-SoC uses fast, incremental, multi-threaded DRC and litho process checking engines to produce a high-quality, robust layout that is litho-friendly and inherently less sensitive to manufacturing variations. Combined with MCMM, Olympus-SoC produces a manufacturable layout without time consuming design iterations.

    Olympus-SoC’s patented virtual timing graph technology enables true multi-corner multi-mode optimization which impacts all aspects of place-and-route. For example, Olympus-SoC considers all modes and corners, and their associated timing windows, when doing signal integrity analysis. (Click to view larger)

  • 100M+ Gate Capacity
    The flexible Olympus-SoC architecture and ultra-compact database support new variability models, a wide range of design styles (including low power layouts), and full-chip optimization for 100M+ gate designs.
  • Ultra-Fine-Grain Parallelization
    Olympus-SoC is the only place-and-route system that provides ultra-fine grain task parallelization of timing, signal integrity, power, area and DFM analysis tasks, allowing it to scale efficiently on multi-core processor platforms with 16-32 CPU cores, reducing design closure time to a minimum.

Physical Verification and Design-for-Manufacturing

  • Industry-Leading Performance
    The Calibre nm Platform is the industry’s leading physical verification and DFM platform, known for delivering best-in-class performance, accuracy, and reliability. A powerful hierarchical geometry engine and database are at the heart of the Calibre tool suite, providing a common foundation for all tapeout-to-mask production steps. Calibre MT, Calibre MTflex and Hyperscaling distributed computing technologies enhance performance and reduce turnaround times across the flow.
  • High-Productivity Workflows
    Our innovative parallel design rule checking and debugging environment speed identification, analysis and corrections of rule violations.
  • Equation-based DRC
    Industry-leading Equation-based DRC technology allows you to accurately measure complex, multi-dimensional structures and apply checks in the form of multivariate functions. This helps you to avoid over-constraining your design, improves performances for complex checks, and makes it easier to create and maintain design rules.
  • PERC
    Programmable Electrical Rule Checking allows you to automate checks for high reliability, such as ESD compliance. It can also be used to enforce unique design guidelines for mixed signal and other complex design styles.

GDSII-to-Mask Technology

  • Unified Platform
    A single platform and litho simulation model supports litho-friendly design, OPC recipe verification, process window analysis and verification, and mask signoff.
  • The Leader Since 130nm
    The Calibre® Tapeout-to-Mask solution has led the way since the 130nm process node. Technology for the 32nm and 22nm nodes is already in development and will be production proven when your commercial manufacturing ramps up. Calibre OPC software provides both sparse and dense simulation allowing you to select the best configuration to meet your needs on a mask layer-by-layer basis.

    The versatile Calibre platform is an innovative combination of common engines, simulation models and control languages, and highly-flexible interfaces crafted to be infinitely adaptable to customers’ unique flow requirements. (Click to view larger)

  • Mask Process Correction
    Mentor also provides unique mask process correction software to address maskwriter imaging issues below 45nm.
  • Performance and Cost Effectiveness
    Our software is optimized to take full advantage of highly parallelized CPUs, such as the Cell Bandwidth Engine (Cell/B.E.) multicore processor, dramatically improving your turnaround time while reducing cost, space and power consumption. Calibre automatically manages task distribution and optimizes the workflow to take best advantage of any mix of specialized and general purpose CPUs.

Silicon Test and Yield Analysis

  • Highest Quality Test with Embedded Compression
    Tessent™ TestKompress® uses embedded deterministic test (EDT™) for delivering high-quality test while lowering cost. TestKompress is the only automatic test pattern generation (ATPG) application that meets the IC industry requirements for scan test compression as specified by the “International Technology Roadmap for Semiconductors.” Mentor’s patented EDT technology provides consistent results for a wide variety of design types from microprocessors to automotive electronics without any loss of fault coverage. Flexible configurations allow TestKompress to work efficiently in any design flow.
  • Powerful, Automated, Layout-Aware Diagnosis Improves Yield Analysis
    Tessent™ Diagnosis performs accurate and high-resolution test failure diagnosis to determine a defect’s most probable failure mechanism, logic location, and physical location.

Manufacturing Variability Challenges

Design

Mentor’s variability-aware/timing-aware place and route system delivers “correct-by-construction” layouts concurrently optimized for both performance and yield across any number of modes and corners.

Enhance

Mentor’s Calibre® platform provides the fastest, most accurate, and most reliable integrated verification, extraction and design-for-manufacturing (DFM) platform for both library cells and full chips.

Fabricate

Mentor’s fast, accurate, and cost-effective mask resolution enhancement and data prep flows ensure quick mask turnaround and high manufacturability at 65 nm, 45 nm, 32 nm and beyond.

Ramp

Mentor’s production yield solution combines the power of diagnosis-driven yield analysis and high-quality manufacturing test to accelerate yield ramp.

Manufacturing Variability Resources

Assessment and comparison of different approaches for mask write time reduction

White Paper: The extension of 193nm exposure wavelength to smaller nodes continues the trend of increased data complexity and subsequently longer mask writing times. We review the data preparation steps post tapeout,... View White Paper

Can fast Rule-Based Assist Feature Generation in random-logic Contact Layout provide sufficient Process Window?

White Paper: Semiconductor manufacturing is continuously ramping up the yield of technology processes with transistor dimensions well below the exposure wave length. Light di raction e ects limit the resolution of pattern... View White Paper

News

View all Manufacturing Variability Resources: White Papers, Datasheets, Web Seminars, and more