Addressing Advanced Process Nodes
The Mentor Graphics Design-to-Silicon Solution for Managing Variability incorporates many unique technologies developed specifically to address issues that arise at advanced process nodes. There is no silver bullet or single-point solution for variability. It takes innovation at every stage of the IC implementation flow.
Digital IC Physical Design (Place and Route)
- Multi-corner Multi-mode
The Olympus-SoC™ system leads the place and route pack with true multi-corner multi-mode (MCMM) analysis and optimization throughout the physical design flow. Our patented method for storing multiple timing graphs as a single representation allows all place-and-route engines and APIs to incorporate MCMM capabilities.
- DFM-Aware Routing
Olympus-SoC uses fast, incremental, multi-threaded DRC and litho process checking engines to produce a high-quality, robust layout that is litho-friendly and inherently less sensitive to manufacturing variations. Combined with MCMM, Olympus-SoC produces a manufacturable layout without time consuming design iterations.
- 100M+ Gate Capacity
The flexible Olympus-SoC architecture and ultra-compact database support new variability models, a wide range of design styles (including low power layouts), and full-chip optimization for 100M+ gate designs.
- Ultra-Fine-Grain Parallelization
Olympus-SoC is the only place-and-route system that provides ultra-fine grain task parallelization of timing, signal integrity, power, area and DFM analysis tasks, allowing it to scale efficiently on multi-core processor platforms with 16-32 CPU cores, reducing design closure time to a minimum.
Physical Verification and Design-for-Manufacturing
- Industry-Leading Performance
The Calibre nm Platform is the industry’s leading physical verification and DFM platform, known for delivering best-in-class performance, accuracy, and reliability. A powerful hierarchical geometry engine and database are at the heart of the Calibre tool suite, providing a common foundation for all tapeout-to-mask production steps. Calibre MT, Calibre MTflex and Hyperscaling distributed computing technologies enhance performance and reduce turnaround times across the flow.
- High-Productivity Workflows
Our innovative parallel design rule checking and debugging environment speed identification, analysis and corrections of rule violations.
- Equation-based DRC
Industry-leading Equation-based DRC technology allows you to accurately measure complex, multi-dimensional structures and apply checks in the form of multivariate functions. This helps you to avoid over-constraining your design, improves performances for complex checks, and makes it easier to create and maintain design rules.
Programmable Electrical Rule Checking allows you to automate checks for high reliability, such as ESD compliance. It can also be used to enforce unique design guidelines for mixed signal and other complex design styles.
- Unified Platform
A single platform and litho simulation model supports litho-friendly design, OPC recipe verification, process window analysis and verification, and mask signoff.
- The Leader Since 130nm
The Calibre® Tapeout-to-Mask solution has led the way since the 130nm process node. Technology for the 32nm and 22nm nodes is already in development and will be production proven when your commercial manufacturing ramps up. Calibre OPC software provides both sparse and dense simulation allowing you to select the best configuration to meet your needs on a mask layer-by-layer basis.
- Mask Process Correction
Mentor also provides unique mask process correction software to address maskwriter imaging issues below 45nm.
- Performance and Cost Effectiveness
Our software is optimized to take full advantage of highly parallelized CPUs, such as the Cell Bandwidth Engine (Cell/B.E.) multicore processor, dramatically improving your turnaround time while reducing cost, space and power consumption. Calibre automatically manages task distribution and optimizes the workflow to take best advantage of any mix of specialized and general purpose CPUs.
Silicon Test and Yield Analysis
- Highest Quality Test with Embedded Compression
Tessent™ TestKompress® uses embedded deterministic test (EDT™) for delivering high-quality test while lowering cost. TestKompress is the only automatic test pattern generation (ATPG) application that meets the IC industry requirements for scan test compression as specified by the “International Technology Roadmap for Semiconductors.” Mentor’s patented EDT technology provides consistent results for a wide variety of design types from microprocessors to automotive electronics without any loss of fault coverage. Flexible configurations allow TestKompress to work efficiently in any design flow.
- Powerful, Automated, Layout-Aware Diagnosis Improves Yield Analysis
Tessent™ Diagnosis performs accurate and high-resolution test failure diagnosis to determine a defect’s most probable failure mechanism, logic location, and physical location.
White Paper: Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known... View White Paper
White Paper: Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem... View White Paper