SystemC Modeling & Verification

Duration: 4 Days
Pricing: 24000 NTD
Course Part Number: 221303

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Description

This four-day class introduces the student to modeling and verification with C/C++ and the SystemC C++ class library including the SystemC Verification library (2.0-SCV). It is intended for engineers who are new to SystemC or those who may be self-taught, with an interest in learning SystemC with a modeling and verification focus. Version 2.0 and SystemC Verification Library concepts are taught.
 
SystemC Functional level and transaction Level (TLM) modeling is covered. Communication refinement methodology and techniques are covered in depth. SystemC Verification concepts are taught.
 
The lecture modules will guide you through the various concepts underlying SystemC verification. Hands-on lab exercises will reinforce lecture topics and provide you with extensive experience under the guidance of our industry expert instructors.

You will learn how to

Write, compile, execute and debug system and hardware descriptions with SystemC.
 

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using SystemC under the guidance of our expert instructors. Hands-on lab topics include:
 

• C++streams, pointers and references, data abstraction
• Module construction
• Channels, time and clocks, module instantiation
• SystemC data types
• Primitive channels
• Data introspection
• Randomization
• Constraints
• Sparse arrays

Audience

Engineers and managers new to SystemC or self-taught with a desire to improve.
 

Prerequisites

Familiarity with Verilog, VHDL or C
 

Key Topics

• Introduction
• SystemC modeling
• Basic modeling structure
• Getting started - running & debugging
• C++ 
  • Streams, pointers and references, data abstraction
  • Data hiding, initialization & cleanup
  • Overloading, const, templates, inheritance
• Modules 
  • Channels, ports, interfaces
  • Module constructor
  • Events
  • Processes in general
  • Thread processes
  • Method processes
  • Module instantiation (in modules)
• sc_main 
  • Channels
  • Time & clocks
  • Module instantiation (in sc_main)
  • Simulation functions
• SystemC data types
• Primitive channels
• User defined channels
• Communication refinement 
  • Channel refinement & adapters
• SystemC Verification 
  • Data Introspection
  • Randomization
  • Constraints
  • Customizing Data Generation
  • Sparse Arrays