IC Station - Accelerating Your Productivity

Duration:  1 day
Pricing:  $6000 NTD
Course Part Number: 051723

Description

Education Services can help you acquire the skills needed to maximize your usage of IC Station and realize its full impact on your layout process. This course will empower you to layout VLSI designs directly from the logic, check them for errors, and keep them current with the latest design changes. The lecture modules will guide you through the various concepts and tools associated with IC Station from the basics of creating polygons to more advanced topics like SDL. Hands-on lab exercises will reinforce lecture topics and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

You will learn how to

• Use ICgraph^TM in both GE (Geometry Editing) and CBC (Correct by Construction) modes
• Harness the power of Schematic Driven Layout (SDL)
• Speed up your process using ICdevice^TM.
• Customize automatically generated devices for your specific layout needs
• Use ICassemble to support every level of SoC design hierarchy-analog and digital 
• Use IC Station routing tools:  Iroute, and ARoute to route leaf cells, sub-blocks, and block cells
• Catch layout errors early in the design process using ICshortchecker, ICverify^TM and ECO
• Use the power of hierarchical design to automatically keep all designs up-to-date
• Customize the user interface so the commands you use most are quickly accessible

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience in using IC Station under the guidance of our expert instructors. Hands-on lab topics include:

• Placing and editing polygons on various layers
• Laying out a hierarchical design using Schematic Driven Layout
• Creating cells "on they fly"
• Routing usingARoute and IRoute
• Checking for shorts using ICshortchecker
• Checking for layout rule violations using ICrules
• Managing hierarchical designs
• Using ICdevice to easily place MOSFETs, resisters, capacitors, vias, and guard bands.
• Editing devices
• Using ICassemble to create and edit block boundaries; to place block pins; to route critical paths and route top-level paths
• Keeping the layout current with the schematic logic using ECO
• Customizing the user interface

Audience

• IC Layout Engineers and Designers
• CAD Engineers and Managers who will be responsible for integrating IC Station into their design flow
• Front-end Design engineers who would like to have a better understanding of the layout process
• Members of CAD support groups who are responsible for increased productivity of VLSI design teams

Prerequisites

• Basic knowledge of IC Layout techniques and procedures (helpful but not required)
• Familiarity with UNIX
  

Course Outline

• Load the ASCII process file
• Open an existing cell
• Reserve a cell for edit
• Place polygons using ICgraph
• Open the layer palette and set the selectability, visibility, and fill for each layer
• Change the view area using ICgraph viewing commands
• View the transcript
• Open the help bookcase and search for help
• Set up the select filter
• Select an object(s)
• Edit object(s)
• Modify paths and path centerlines
• Use Boolean operations on objects
• Add and change text and property text
• Use the ICgraph design management tool to copy and move designs
• Set up a cell for SDL
• Use DLA Layout to place layout instances
• Place ports/schematic nets
• Use ARoute to route leaf cells
• Use ICshortchecker to find shorts
• Add cells to a hierarchy
• Use peek to change the visible layers of a hierarchy
• Change editing context and view context
• Handle references and referenced cells
• Flatten a cell
• Create and edit arrays
• Update hierarchical designs
• Load a rule file
• Verify connectivity of your layout against the original schematic with ICtrace
• Verify the layout against DRC rulechecks with ICrules
• Define block boundaries with ICassemble
• Edit block boundaries
• Automatically place block pins for hierarchical blocks
• Use IRoute to interactively route sub-blocks
• Use ARoute to route block-level hierarchy
• Read in a Verilog netlist into a block
• Use AutoCells to place and route
• Add MOS devices to your layout
• Create MOS device subtypes using an initial MOS device as a starting point
• Edit MOS devices
• Explain the MOS pin naming conventions
• Create and edit point-based capacitor devices
• Explain capacitor pin naming conventions
• Create, connect and edit multiple resistors
• Create a point-based via device
• Place a shape-based guard band around a defined layout region
• Use ECO
• Change layer appearance in ICgraph
• Create and edit strokes
• Add functions to ICgraph pulldown, popup, palette menus, and strokes
• Register 3-2-1 commands
• Add softkeys